ATE529864T1 - Pseudo-doppelportspeicher mit taktzyklusunabhängigem verhältnis zwischen erstem und zweitem speicherzugang - Google Patents

Pseudo-doppelportspeicher mit taktzyklusunabhängigem verhältnis zwischen erstem und zweitem speicherzugang

Info

Publication number
ATE529864T1
ATE529864T1 AT06850170T AT06850170T ATE529864T1 AT E529864 T1 ATE529864 T1 AT E529864T1 AT 06850170 T AT06850170 T AT 06850170T AT 06850170 T AT06850170 T AT 06850170T AT E529864 T1 ATE529864 T1 AT E529864T1
Authority
AT
Austria
Prior art keywords
memory access
delay
memory
dual port
depends
Prior art date
Application number
AT06850170T
Other languages
English (en)
Inventor
Chang Ho Jung
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE529864T1 publication Critical patent/ATE529864T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
AT06850170T 2005-11-17 2006-11-17 Pseudo-doppelportspeicher mit taktzyklusunabhängigem verhältnis zwischen erstem und zweitem speicherzugang ATE529864T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/282,333 US7251193B2 (en) 2005-11-17 2005-11-17 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent
PCT/US2006/061060 WO2007114858A2 (en) 2005-11-17 2006-11-17 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent

Publications (1)

Publication Number Publication Date
ATE529864T1 true ATE529864T1 (de) 2011-11-15

Family

ID=38040657

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06850170T ATE529864T1 (de) 2005-11-17 2006-11-17 Pseudo-doppelportspeicher mit taktzyklusunabhängigem verhältnis zwischen erstem und zweitem speicherzugang

Country Status (8)

Country Link
US (1) US7251193B2 (de)
EP (1) EP1949381B1 (de)
KR (1) KR100962756B1 (de)
CN (1) CN101356586A (de)
AT (1) ATE529864T1 (de)
CA (1) CA2632615A1 (de)
RU (1) RU2008124181A (de)
WO (1) WO2007114858A2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8756521B1 (en) 2004-09-30 2014-06-17 Rockwell Automation Technologies, Inc. Systems and methods for automatic visualization configuration
US8799800B2 (en) 2005-05-13 2014-08-05 Rockwell Automation Technologies, Inc. Automatic user interface generation
US7650405B2 (en) * 2005-05-13 2010-01-19 Rockwell Automation Technologies, Inc. Tracking and tracing across process boundaries in an industrial automation environment
US20080298137A1 (en) * 2007-03-22 2008-12-04 Yuen Hung Chan Method and structure for domino read bit line and set reset latch
US7890789B2 (en) * 2007-12-12 2011-02-15 Broadcom Corporation Circuit and method for generation of duty cycle independent core clock
US7760562B2 (en) * 2008-03-13 2010-07-20 Qualcomm Incorporated Address multiplexing in pseudo-dual port memory
US8370557B2 (en) * 2008-12-19 2013-02-05 Intel Corporation Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory
US8045401B2 (en) * 2009-09-18 2011-10-25 Arm Limited Supporting scan functions within memories
CN102110464B (zh) * 2009-12-26 2015-06-10 上海芯豪微电子有限公司 宽带读写存储器装置
US8848412B1 (en) * 2013-07-05 2014-09-30 Arm Limited Ternary content addressable memory
US9324416B2 (en) * 2014-08-20 2016-04-26 Qualcomm Incorporated Pseudo dual port memory with dual latch flip-flop
US10061542B2 (en) * 2015-09-15 2018-08-28 Qualcomm Incorporated Pseudo dual port memory
GB201603589D0 (en) * 2016-03-01 2016-04-13 Surecore Ltd Memory unit
JP6682367B2 (ja) * 2016-06-08 2020-04-15 ルネサスエレクトロニクス株式会社 マルチポートメモリ、メモリマクロおよび半導体装置
JP6637872B2 (ja) * 2016-10-28 2020-01-29 ルネサスエレクトロニクス株式会社 マルチポートメモリおよび半導体装置
US10032506B2 (en) 2016-12-12 2018-07-24 Stmicroelectronics International N.V. Configurable pseudo dual port architecture for use with single port SRAM
US9928889B1 (en) * 2017-03-21 2018-03-27 Qualcomm Incorporation Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories
US11133049B2 (en) * 2018-06-21 2021-09-28 Tc Lab, Inc. 3D memory array clusters and resulting memory architecture
CN110248102B (zh) * 2019-07-22 2021-01-15 中国大恒(集团)有限公司北京图像视觉技术分公司 一种工业相机缓冲方法
US11024347B2 (en) * 2019-10-17 2021-06-01 Marvell Asia Pte, Ltd. Multiple sense amplifier and data path-based pseudo dual port SRAM
CN111341376B (zh) * 2020-03-11 2022-06-24 展讯通信（上海）有限公司 Sram时序测试电路及测试方法
US11676657B2 (en) * 2020-04-16 2023-06-13 Mediatek Inc. Time-interleaving sensing scheme for pseudo dual-port memory
US11442875B2 (en) * 2020-05-18 2022-09-13 Integrated Silicon Solution, (Cayman) Inc. Arbitration control for pseudostatic random access memory device
CN114496027B (zh) * 2020-10-26 2026-01-30 中芯国际集成电路制造(上海)有限公司 混合端口存储器及其工作方法
KR20220138961A (ko) 2021-04-07 2022-10-14 에스케이하이닉스 주식회사 메모리 장치 및 메모리 장치의 동작 방법
CN113764012B (zh) * 2021-08-19 2022-04-22 北京中科胜芯科技有限公司 一种可调刷新速率的双端口存储器
KR20240079439A (ko) * 2022-11-29 2024-06-05 삼성전자주식회사 반도체 메모리 장치 및 그것의 동작 방법
CN118538263A (zh) * 2024-07-25 2024-08-23 中科亿海微电子科技（苏州）有限公司 一种对fpga bram读写冲突的时序控制方法及电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4018159B2 (ja) * 1993-06-28 2007-12-05 株式会社ルネサステクノロジ 半導体集積回路
KR0142968B1 (ko) * 1995-06-30 1998-08-17 김광호 반도체 메모리 장치의 클럭 발생 장치
US5781480A (en) * 1997-07-29 1998-07-14 Motorola, Inc. Pipelined dual port integrated circuit memory
US6882562B2 (en) * 2001-11-01 2005-04-19 Agilent Technologies, Inc. Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell
US6917536B1 (en) * 2002-09-13 2005-07-12 Lattice Semiconductor Corporation Memory access circuit and method for reading and writing data with the same clock signal

Also Published As

Publication number Publication date
KR20080080548A (ko) 2008-09-04
CA2632615A1 (en) 2007-10-11
KR100962756B1 (ko) 2010-06-09
WO2007114858A2 (en) 2007-10-11
EP1949381B1 (de) 2011-10-19
US20070109909A1 (en) 2007-05-17
WO2007114858A3 (en) 2008-03-13
CN101356586A (zh) 2009-01-28
EP1949381A2 (de) 2008-07-30
RU2008124181A (ru) 2009-12-27
US7251193B2 (en) 2007-07-31

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