ATE530984T1 - Dynamischer konfigurierbarer texturzwischenspeicher für multitexturierung - Google Patents

Dynamischer konfigurierbarer texturzwischenspeicher für multitexturierung

Info

Publication number
ATE530984T1
ATE530984T1 AT08743505T AT08743505T ATE530984T1 AT E530984 T1 ATE530984 T1 AT E530984T1 AT 08743505 T AT08743505 T AT 08743505T AT 08743505 T AT08743505 T AT 08743505T AT E530984 T1 ATE530984 T1 AT E530984T1
Authority
AT
Austria
Prior art keywords
texture cache
multitexturing
texture
cache
dynamic configurable
Prior art date
Application number
AT08743505T
Other languages
English (en)
Inventor
Chun Yu
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE530984T1 publication Critical patent/ATE530984T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Generation (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT08743505T 2007-02-22 2008-02-20 Dynamischer konfigurierbarer texturzwischenspeicher für multitexturierung ATE530984T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/677,986 US8022960B2 (en) 2007-02-22 2007-02-22 Dynamic configurable texture cache for multi-texturing
PCT/US2008/054452 WO2008103750A2 (en) 2007-02-22 2008-02-20 Dynamic configurable texture cache for multi-texturing

Publications (1)

Publication Number Publication Date
ATE530984T1 true ATE530984T1 (de) 2011-11-15

Family

ID=39708707

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08743505T ATE530984T1 (de) 2007-02-22 2008-02-20 Dynamischer konfigurierbarer texturzwischenspeicher für multitexturierung

Country Status (9)

Country Link
US (1) US8022960B2 (de)
EP (1) EP2113103B1 (de)
JP (1) JP5113196B2 (de)
KR (1) KR101097085B1 (de)
CN (1) CN101583929B (de)
AT (1) ATE530984T1 (de)
CA (1) CA2672037A1 (de)
TW (1) TW200849012A (de)
WO (1) WO2008103750A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8117541B2 (en) * 2007-03-06 2012-02-14 Wildtangent, Inc. Rendering of two-dimensional markup messages
JP2010146205A (ja) * 2008-12-17 2010-07-01 Toshiba Corp キャッシュメモリ装置及び画像処理装置
TWI420311B (zh) * 2010-03-18 2013-12-21 Univ Nat Sun Yat Sen 基於集合分模組之快取記憶體之分割方法
US9563932B2 (en) * 2011-01-28 2017-02-07 Intel Corporation Techniques to request stored data from memory
WO2012109770A1 (en) * 2011-02-18 2012-08-23 Intel Corporation (A Corporation Of Delaware) Techniques to request stored data from a memory
CN103034465B (zh) * 2011-09-29 2016-04-27 腾讯科技（深圳）有限公司 图像浏览方法及浏览系统
KR101862785B1 (ko) 2011-10-17 2018-07-06 삼성전자주식회사 타일 기반 렌더링을 위한 캐쉬 메모리 시스템 및 캐슁 방법
CN103077129B (zh) * 2012-12-31 2016-07-13 上海算芯微电子有限公司 信息处理方法与装置
CN103077130B (zh) * 2012-12-31 2016-03-16 上海算芯微电子有限公司 信息处理方法及装置
KR102100161B1 (ko) 2014-02-04 2020-04-14 삼성전자주식회사 Gpu 데이터 캐싱 방법 및 그에 따른 데이터 프로세싱 시스템

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2646854B2 (ja) * 1990-12-18 1997-08-27 三菱電機株式会社 マイクロプロセッサ
US5367653A (en) * 1991-12-26 1994-11-22 International Business Machines Corporation Reconfigurable multi-way associative cache memory
US5801708A (en) 1995-06-06 1998-09-01 Hewlett-Packard Company MIP map texture storage by dividing and allocating among multiple blocks
JP3586991B2 (ja) * 1996-08-30 2004-11-10 ソニー株式会社 テクスチャ・データ読出装置およびレンダリング装置
US6002410A (en) * 1997-08-25 1999-12-14 Chromatic Research, Inc. Reconfigurable texture cache
CA2301755C (en) 1997-08-26 2007-11-13 Stresshead Ag Reinforcement device for supporting structures
US6750872B1 (en) 1999-09-17 2004-06-15 S3 Graphics, Co., Ltd. Dynamic allocation of texture cache memory
US7069387B2 (en) * 2003-03-31 2006-06-27 Sun Microsystems, Inc. Optimized cache structure for multi-texturing
JP2005025254A (ja) * 2003-06-30 2005-01-27 Toshiba Corp コンピュータグラフィックス描画装置
US7127560B2 (en) * 2003-10-14 2006-10-24 International Business Machines Corporation Method of dynamically controlling cache size
US7483035B2 (en) 2005-07-07 2009-01-27 Via Technologies, Inc. Texture cache control using a data dependent slot selection scheme
US8035650B2 (en) * 2006-07-25 2011-10-11 Qualcomm Incorporated Tiled cache for multiple software programs

Also Published As

Publication number Publication date
CN101583929B (zh) 2012-06-27
US8022960B2 (en) 2011-09-20
US20080204466A1 (en) 2008-08-28
CA2672037A1 (en) 2008-08-28
WO2008103750A3 (en) 2008-11-27
TW200849012A (en) 2008-12-16
JP5113196B2 (ja) 2013-01-09
KR20090097899A (ko) 2009-09-16
WO2008103750A2 (en) 2008-08-28
EP2113103A2 (de) 2009-11-04
JP2010519651A (ja) 2010-06-03
EP2113103B1 (de) 2011-10-26
KR101097085B1 (ko) 2011-12-22
CN101583929A (zh) 2009-11-18

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