ATE531048T1 - Nicht flüchtiger speicher mit hintergrund- datensperren-caching während leseoperationen und entsprechende verfahren - Google Patents

Nicht flüchtiger speicher mit hintergrund- datensperren-caching während leseoperationen und entsprechende verfahren

Info

Publication number
ATE531048T1
ATE531048T1 AT07783139T AT07783139T ATE531048T1 AT E531048 T1 ATE531048 T1 AT E531048T1 AT 07783139 T AT07783139 T AT 07783139T AT 07783139 T AT07783139 T AT 07783139T AT E531048 T1 ATE531048 T1 AT E531048T1
Authority
AT
Austria
Prior art keywords
read
data
memory
volatile memory
caching
Prior art date
Application number
AT07783139T
Other languages
English (en)
Inventor
Yan Li
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/381,997 external-priority patent/US7480181B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Priority claimed from PCT/US2007/068069 external-priority patent/WO2007131062A2/en
Application granted granted Critical
Publication of ATE531048T1 publication Critical patent/ATE531048T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Lock And Its Accessories (AREA)
  • Electrophonic Musical Instruments (AREA)
AT07783139T 2006-05-05 2007-05-02 Nicht flüchtiger speicher mit hintergrund- datensperren-caching während leseoperationen und entsprechende verfahren ATE531048T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/381,994 US7447078B2 (en) 2005-04-01 2006-05-05 Method for non-volatile memory with background data latch caching during read operations
US11/381,997 US7480181B2 (en) 2005-04-01 2006-05-05 Non-volatile memory with background data latch caching during read operations
PCT/US2007/068069 WO2007131062A2 (en) 2006-05-05 2007-05-02 Non-volatile memory with background data latch caching during read operations and methods therefor

Publications (1)

Publication Number Publication Date
ATE531048T1 true ATE531048T1 (de) 2011-11-15

Family

ID=40227503

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07783139T ATE531048T1 (de) 2006-05-05 2007-05-02 Nicht flüchtiger speicher mit hintergrund- datensperren-caching während leseoperationen und entsprechende verfahren

Country Status (6)

Country Link
US (1) US7447078B2 (de)
JP (1) JP4814995B2 (de)
KR (1) KR101400999B1 (de)
CN (1) CN101438353B (de)
AT (1) ATE531048T1 (de)
TW (1) TWI348699B (de)

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KR101400999B1 (ko) 2014-05-29
CN101438353B (zh) 2012-10-03
US20060221696A1 (en) 2006-10-05
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