ATE532288T1 - Takt- und datenwiederherstellungsverfahren und - vorrichtung - Google Patents

Takt- und datenwiederherstellungsverfahren und - vorrichtung

Info

Publication number
ATE532288T1
ATE532288T1 AT04717377T AT04717377T ATE532288T1 AT E532288 T1 ATE532288 T1 AT E532288T1 AT 04717377 T AT04717377 T AT 04717377T AT 04717377 T AT04717377 T AT 04717377T AT E532288 T1 ATE532288 T1 AT E532288T1
Authority
AT
Austria
Prior art keywords
clock
sequence
recovery method
data recovery
time
Prior art date
Application number
AT04717377T
Other languages
English (en)
Inventor
Daniel Allen
Original Assignee
Timelab Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Timelab Corp filed Critical Timelab Corp
Application granted granted Critical
Publication of ATE532288T1 publication Critical patent/ATE532288T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT04717377T 2003-03-04 2004-03-04 Takt- und datenwiederherstellungsverfahren und - vorrichtung ATE532288T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45179903P 2003-03-04 2003-03-04
PCT/US2004/006510 WO2004079911A2 (en) 2003-03-04 2004-03-04 Clock and data recovery method and apparatus

Publications (1)

Publication Number Publication Date
ATE532288T1 true ATE532288T1 (de) 2011-11-15

Family

ID=32962638

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04717377T ATE532288T1 (de) 2003-03-04 2004-03-04 Takt- und datenwiederherstellungsverfahren und - vorrichtung

Country Status (8)

Country Link
US (1) US7613263B2 (de)
EP (1) EP1599963B1 (de)
JP (1) JP2006520169A (de)
KR (1) KR101107849B1 (de)
CN (1) CN1802810B (de)
AT (1) ATE532288T1 (de)
CA (1) CA2518071A1 (de)
WO (1) WO2004079911A2 (de)

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TWI370622B (en) * 2004-02-09 2012-08-11 Altera Corp Method, device and serializer-deserializer system for serial transfer of bits and method and deserializer for recovering bits at a destination
US7339853B2 (en) * 2005-12-02 2008-03-04 Agilent Technologies, Inc. Time stamping events for fractions of a clock cycle
US7577221B2 (en) * 2006-03-01 2009-08-18 Alcatel-Lucent Usa Inc. Receiver scheme for synchronous digital transmission
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US8098692B2 (en) * 2006-08-29 2012-01-17 Koninklijke Philips Electronics N.V. Method and apparatus for high speed LVDS communication
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US9277515B2 (en) * 2013-11-04 2016-03-01 Samsung Electronics Co., Ltd Precise time tagging of events over an imprecise link
US9426082B2 (en) * 2014-01-03 2016-08-23 Qualcomm Incorporated Low-voltage differential signaling or 2-wire differential link with symbol transition clocking
CN105337591B (zh) * 2014-05-26 2017-12-22 无锡华润矽科微电子有限公司 基于usb设备实现时钟恢复的电路结构及方法
TWI542155B (zh) * 2014-07-02 2016-07-11 瑞昱半導體股份有限公司 時脈產生器、通訊裝置與循序時脈閘控電路
US9485080B1 (en) 2015-09-01 2016-11-01 Qualcomm Incorporated Multiphase clock data recovery circuit calibration
US10326627B2 (en) * 2016-09-08 2019-06-18 Lattice Semiconductor Corporation Clock recovery and data recovery for programmable logic devices
CN107547188B (zh) * 2017-08-02 2020-04-24 北京东土军悦科技有限公司 一种时钟恢复方法及装置
CN110389976B (zh) * 2018-04-13 2022-04-12 北京京东乾石科技有限公司 一种多接口数据的调度方法和装置
US11906585B2 (en) * 2021-12-16 2024-02-20 Samsung Electronics Co., Ltd. Methods and systems for performing built-in-self-test operations without a dedicated clock source

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Also Published As

Publication number Publication date
EP1599963A4 (de) 2006-05-31
KR101107849B1 (ko) 2012-01-31
EP1599963A2 (de) 2005-11-30
JP2006520169A (ja) 2006-08-31
EP1599963B1 (de) 2011-11-02
WO2004079911A3 (en) 2005-04-28
KR20050122204A (ko) 2005-12-28
US7613263B2 (en) 2009-11-03
WO2004079911A2 (en) 2004-09-16
CN1802810A (zh) 2006-07-12
CA2518071A1 (en) 2004-09-16
CN1802810B (zh) 2010-09-22
US20040264612A1 (en) 2004-12-30

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