ATE532329T1 - Multiviewer-videosystem mit dma-registern und multiport-block-ram sowie entsprechende verfahren - Google Patents

Multiviewer-videosystem mit dma-registern und multiport-block-ram sowie entsprechende verfahren

Info

Publication number
ATE532329T1
ATE532329T1 AT09730475T AT09730475T ATE532329T1 AT E532329 T1 ATE532329 T1 AT E532329T1 AT 09730475 T AT09730475 T AT 09730475T AT 09730475 T AT09730475 T AT 09730475T AT E532329 T1 ATE532329 T1 AT E532329T1
Authority
AT
Austria
Prior art keywords
video data
gpu
memory
dma
video
Prior art date
Application number
AT09730475T
Other languages
English (en)
Inventor
Cristian Camer
Marcin Komorowski
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Application granted granted Critical
Publication of ATE532329T1 publication Critical patent/ATE532329T1/de

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/47End-user applications
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006Details of the interface to the display terminal
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14Display of multiple viewports
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363Graphics controllers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/395Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41Structure of client; Structure of client peripherals
    • H04N21/426Internal components of the client ; Characteristics thereof
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41Structure of client; Structure of client peripherals
    • H04N21/426Internal components of the client ; Characteristics thereof
    • H04N21/42653Internal components of the client ; Characteristics thereof for processing graphics
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/431Generation of visual interfaces for content selection or interaction; Content or additional data rendering
    • H04N21/4312Generation of visual interfaces for content selection or interaction; Content or additional data rendering involving specific graphical features, e.g. screen layout, special fonts or colors, blinking icons, highlights or animations
    • H04N21/4316Generation of visual interfaces for content selection or interaction; Content or additional data rendering involving specific graphical features, e.g. screen layout, special fonts or colors, blinking icons, highlights or animations for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440263Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/44504Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/04Changes in size, position or resolution of an image
    • G09G2340/0407Resolution change, inclusive of the use of different resolutions for different screen areas
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00Parallel handling of streams of display data
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/126The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00Aspects of data communication
    • G09G2370/10Use of a protocol of communication by packets in interfaces along the display data pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Business, Economics & Management (AREA)
  • Marketing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Bus Control (AREA)
AT09730475T 2008-04-08 2009-04-08 Multiviewer-videosystem mit dma-registern und multiport-block-ram sowie entsprechende verfahren ATE532329T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/099,380 US9438844B2 (en) 2008-04-08 2008-04-08 Video multiviewer system using direct memory access (DMA) registers and block RAM
PCT/US2009/039856 WO2009126679A1 (en) 2008-04-08 2009-04-08 Video multiviewer system using direct memory access (dma) registers and multi ported block ram and related method

Publications (1)

Publication Number Publication Date
ATE532329T1 true ATE532329T1 (de) 2011-11-15

Family

ID=40775163

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09730475T ATE532329T1 (de) 2008-04-08 2009-04-08 Multiviewer-videosystem mit dma-registern und multiport-block-ram sowie entsprechende verfahren

Country Status (5)

Country Link
US (1) US9438844B2 (de)
EP (1) EP2274908B1 (de)
AT (1) ATE532329T1 (de)
CA (1) CA2661678C (de)
WO (1) WO2009126679A1 (de)

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US9716854B2 (en) * 2008-04-09 2017-07-25 Imagine Communications Corp. Video multiviewer system with distributed scaling and related methods
CN101859334B (zh) * 2010-05-17 2012-06-13 山东大学 视频解码模块与视频显示处理模块的互联缓存结构设计方法
US9076259B2 (en) 2011-09-14 2015-07-07 Imagine Communications Corp Geospatial multiviewer
US9304730B2 (en) 2012-08-23 2016-04-05 Microsoft Technology Licensing, Llc Direct communication between GPU and FPGA components
CN102905056B (zh) * 2012-10-18 2015-09-02 利亚德光电股份有限公司 视频图像处理方法及装置
US20140267395A1 (en) * 2013-03-13 2014-09-18 Ross Video Limited Low-latency interactive multiviewer interfaces and methods for video broadcast equipment
CN105430303B (zh) * 2015-11-10 2019-05-17 恒宇信通航空装备(北京)股份有限公司 一种军用机载座舱显示系统中基于fpga的图形加速器
US10555010B2 (en) 2016-08-24 2020-02-04 Liquidsky Software, Inc. Network-enabled graphics processing module
CN106776373B (zh) * 2017-01-12 2020-10-16 合肥速显微电子科技有限公司 一种面向移动设备的基于闪存的高速缓存系统及方法
US10332235B1 (en) 2018-05-01 2019-06-25 At&T Intellectual Property I, L.P. Direct memory access for graphics processing unit packet processing
US10795840B2 (en) 2018-11-12 2020-10-06 At&T Intellectual Property I, L.P. Persistent kernel for graphics processing unit direct memory access network packet processing
CN115658571B (zh) * 2022-11-16 2023-02-28 浪潮电子信息产业股份有限公司 一种数据传输方法、装置、电子设备及介质
US12591447B2 (en) 2024-01-25 2026-03-31 Parry Labs, Llc Hardware apparatus for isolated virtual environments
US12062112B1 (en) 2024-01-25 2024-08-13 Parry Labs, Llc Apparatus for heterogenous processing

Family Cites Families (14)

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US5099331A (en) * 1987-09-04 1992-03-24 Texas Instruments Incorporated Apparatus for overlaying a displayed image with a second image
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels
US5420984A (en) * 1992-06-30 1995-05-30 Genroco, Inc. Apparatus and method for rapid switching between control of first and second DMA circuitry to effect rapid switching beween DMA communications
US5848264A (en) * 1996-10-25 1998-12-08 S3 Incorporated Debug and video queue for multi-processor chip
US5978866A (en) * 1997-03-10 1999-11-02 Integrated Technology Express, Inc. Distributed pre-fetch buffer for multiple DMA channel device
US5933855A (en) * 1997-03-21 1999-08-03 Rubinstein; Richard Shared, reconfigurable memory architectures for digital signal processing
US6895452B1 (en) * 1997-06-04 2005-05-17 Marger Johnson & Mccollom, P.C. Tightly coupled and scalable memory and execution unit architecture
WO2000028518A2 (en) * 1998-11-09 2000-05-18 Broadcom Corporation Graphics display system
JP2002112992A (ja) * 2000-06-30 2002-04-16 Canon Inc 信号処理装置及び方法、及び撮像装置
CA2379782C (en) * 2001-04-20 2010-11-02 Evertz Microsystems Ltd. Circuit and method for live switching of digital video programs containing embedded audio data
US6963348B2 (en) * 2002-05-31 2005-11-08 Nvidia Corporation Method and apparatus for display image adjustment
US7456851B2 (en) * 2003-05-20 2008-11-25 Honeywell International Inc. Method and apparatus for spatial compensation for pixel pattern on LCD displays
US20070268317A1 (en) * 2006-05-18 2007-11-22 Dan Banay User interface system and method for selectively displaying a portion of a display screen
US7536669B1 (en) * 2006-08-30 2009-05-19 Xilinx, Inc. Generic DMA IP core interface for FPGA platform design

Also Published As

Publication number Publication date
CA2661678A1 (en) 2009-10-08
WO2009126679A1 (en) 2009-10-15
EP2274908A1 (de) 2011-01-19
EP2274908B1 (de) 2011-11-02
CA2661678C (en) 2014-09-09
US20090254683A1 (en) 2009-10-08
US9438844B2 (en) 2016-09-06

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