ATE534144T1 - Wafer mit schreibspuren mit externen pads und/oder aktiven schaltungen zum matrizenprüfen - Google Patents

Wafer mit schreibspuren mit externen pads und/oder aktiven schaltungen zum matrizenprüfen

Info

Publication number
ATE534144T1
ATE534144T1 AT06809399T AT06809399T ATE534144T1 AT E534144 T1 ATE534144 T1 AT E534144T1 AT 06809399 T AT06809399 T AT 06809399T AT 06809399 T AT06809399 T AT 06809399T AT E534144 T1 ATE534144 T1 AT E534144T1
Authority
AT
Austria
Prior art keywords
pads
internal
die
integrated components
group
Prior art date
Application number
AT06809399T
Other languages
English (en)
Inventor
Herve Marie
Sofiane Ellouz
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE534144T1 publication Critical patent/ATE534144T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
AT06809399T 2005-09-27 2006-09-25 Wafer mit schreibspuren mit externen pads und/oder aktiven schaltungen zum matrizenprüfen ATE534144T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05300778 2005-09-27
PCT/IB2006/053476 WO2007036867A2 (en) 2005-09-27 2006-09-25 Wafer with scribe lanes comprising external pads and/or active circuits for die testing

Publications (1)

Publication Number Publication Date
ATE534144T1 true ATE534144T1 (de) 2011-12-15

Family

ID=37626229

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06809399T ATE534144T1 (de) 2005-09-27 2006-09-25 Wafer mit schreibspuren mit externen pads und/oder aktiven schaltungen zum matrizenprüfen

Country Status (6)

Country Link
US (1) US8173448B2 (de)
EP (1) EP1932176B1 (de)
JP (1) JP2009516908A (de)
CN (1) CN101273454B (de)
AT (1) ATE534144T1 (de)
WO (1) WO2007036867A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007057689A1 (de) 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Chipgebiet, das für eine aluminiumfreie Lothöckerverbindung gestaltet ist, und eine Teststruktur, die für eine aluminiumfreie Drahtverbindung gestaltet ist
CN102177582B (zh) * 2008-08-07 2014-07-09 意法半导体股份有限公司 用于在测试集成在半导体晶片上的多个电子器件期间并行供应电力的电路
EP2290686A3 (de) 2009-08-28 2011-04-20 STMicroelectronics S.r.l. Verfahren zum elektrischen Testen und zur Montage elektronischer Bauelemente
FR2976403B1 (fr) * 2011-06-09 2013-11-22 St Microelectronics Rousset Procede de fabrication d'un circuit integre depourvu de plage de contact de masse
KR102657544B1 (ko) * 2016-09-05 2024-04-16 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 반도체 시스템
EP3557610B1 (de) 2018-04-17 2025-11-05 Infineon Technologies Austria AG Halbleiterscheibe und verfahren zur herstellung einer halbleiterscheibe
CN114660434B (zh) * 2020-12-23 2025-04-01 财团法人工业技术研究院 微集成电路大规模测试
TWI759253B (zh) * 2021-10-22 2022-03-21 黃天興 半導體圖案化製程方法及用於監控半導體圖案化製程的檢測圖案
JP2024524319A (ja) 2021-06-25 2024-07-05 アイシー アナリティカ，エルエルシー 試験回路上の正確な電圧を設定するための装置および方法
WO2022272032A1 (en) * 2021-06-25 2022-12-29 Ic Analytica, Llc Apparatus and method for probing multiple test circuits in wafer scribe lines
TWI847231B (zh) * 2021-10-01 2024-07-01 致茂電子股份有限公司 晶圓檢測方法與檢測設備

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US6124143A (en) * 1998-01-26 2000-09-26 Lsi Logic Corporation Process monitor circuitry for integrated circuits
US20030034489A1 (en) * 2001-08-16 2003-02-20 Broadcom Corporation Apparatus and method for a production testline to monitor CMOS SRAMs
JP5340538B2 (ja) * 2003-08-25 2013-11-13 タウ−メトリックス インコーポレイテッド 半導体コンポーネントとウエハの製造を評価するための手法
US6939727B1 (en) * 2003-11-03 2005-09-06 Lsi Logic Corporation Method for performing statistical post processing in semiconductor manufacturing using ID cells
US7118989B2 (en) * 2004-08-20 2006-10-10 Intel Corporation Method of forming vias on a wafer stack using laser ablation

Also Published As

Publication number Publication date
JP2009516908A (ja) 2009-04-23
US8173448B2 (en) 2012-05-08
WO2007036867A2 (en) 2007-04-05
WO2007036867A3 (en) 2007-07-19
EP1932176B1 (de) 2011-11-16
CN101273454B (zh) 2010-06-23
CN101273454A (zh) 2008-09-24
EP1932176A2 (de) 2008-06-18
US20090127553A1 (en) 2009-05-21

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