ATE535071T1 - Datenreinigung mit einem asynchronen referenztakt - Google Patents

Datenreinigung mit einem asynchronen referenztakt

Info

Publication number
ATE535071T1
ATE535071T1 AT06739274T AT06739274T ATE535071T1 AT E535071 T1 ATE535071 T1 AT E535071T1 AT 06739274 T AT06739274 T AT 06739274T AT 06739274 T AT06739274 T AT 06739274T AT E535071 T1 ATE535071 T1 AT E535071T1
Authority
AT
Austria
Prior art keywords
reference clock
data cleaning
asynchronous reference
jitter
architecture
Prior art date
Application number
AT06739274T
Other languages
English (en)
Inventor
Adam Eldredge
Yunteng Huang
Original Assignee
Silicon Lab Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Lab Inc filed Critical Silicon Lab Inc
Application granted granted Critical
Publication of ATE535071T1 publication Critical patent/ATE535071T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
AT06739274T 2005-03-30 2006-03-22 Datenreinigung mit einem asynchronen referenztakt ATE535071T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/093,903 US7512203B2 (en) 2005-03-30 2005-03-30 Data cleaning with an asynchronous reference clock
PCT/US2006/010414 WO2006104808A1 (en) 2005-03-30 2006-03-22 Data cleaning with an asynchronous reference clock

Publications (1)

Publication Number Publication Date
ATE535071T1 true ATE535071T1 (de) 2011-12-15

Family

ID=36636560

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06739274T ATE535071T1 (de) 2005-03-30 2006-03-22 Datenreinigung mit einem asynchronen referenztakt

Country Status (7)

Country Link
US (1) US7512203B2 (de)
EP (1) EP1867092B1 (de)
JP (1) JP2008535387A (de)
CN (1) CN101151838B (de)
AT (1) ATE535071T1 (de)
TW (1) TW200640146A (de)
WO (1) WO2006104808A1 (de)

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JP4930085B2 (ja) * 2007-02-08 2012-05-09 株式会社富士通ゼネラル 位相検出方法、位相検出装置、同期モータの制御方法、および同期モータの制御装置
US7778371B2 (en) * 2007-03-12 2010-08-17 Applied Micro Circuits Corporation Digitally clock with selectable frequency and duty cycle
JP2008227792A (ja) * 2007-03-12 2008-09-25 Nec Corp トランスポンダ、伝送システム、伝送方法及び伝送プログラム
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JP5537192B2 (ja) * 2010-03-04 2014-07-02 スパンション エルエルシー 受信装置及びゲイン設定方法
US9374648B2 (en) 2010-04-22 2016-06-21 Sonova Ag Hearing assistance system and method
WO2011131241A1 (en) * 2010-04-22 2011-10-27 Phonak Ag Hearing assistance system and method
JP5540906B2 (ja) * 2010-06-03 2014-07-02 富士通セミコンダクター株式会社 データ受信回路
JP2012049863A (ja) 2010-08-27 2012-03-08 Renesas Electronics Corp 半導体装置
US8373481B2 (en) * 2010-12-20 2013-02-12 National Semiconductor Corporation Spur reduction technique for sampling PLL's
TWI451700B (zh) * 2011-12-05 2014-09-01 Global Unichip Corp 時脈資料回復電路
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
US9197403B2 (en) * 2012-07-20 2015-11-24 Freescale Semiconductor, Inc. Calibration arrangement for frequency synthesizers
US8958513B1 (en) * 2013-03-15 2015-02-17 Xilinx, Inc. Clock and data recovery with infinite pull-in range
CN103414452B (zh) * 2013-07-23 2016-08-24 华为技术有限公司 时钟数据恢复装置及电子设备
CN103490773A (zh) * 2013-09-04 2014-01-01 苏州苏尔达信息科技有限公司 一种线性相位比较器数字锁相环电路
US9937124B2 (en) 2014-09-11 2018-04-10 International Business Machines Corporation Microchip substance delivery devices having low-power electromechanical release mechanisms
TWI551082B (zh) * 2014-12-26 2016-09-21 Intelligent transmission system with automatic measurement function and its measurement method
US9755701B2 (en) * 2015-03-31 2017-09-05 International Business Machines Corporation Hybrid tag for radio frequency identification system
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CN105281765B (zh) * 2015-10-23 2018-08-21 东南大学 一种低相位噪声、低功耗差分多模分频器
US10881788B2 (en) 2015-10-30 2021-01-05 International Business Machines Corporation Delivery device including reactive material for programmable discrete delivery of a substance
JP6713786B2 (ja) * 2016-02-26 2020-06-24 ザインエレクトロニクス株式会社 受信装置
US10243671B1 (en) * 2017-10-27 2019-03-26 Ciena Corporation Clock recovery circuits, systems and implementation for increased optical channel density
US10122527B1 (en) * 2018-03-23 2018-11-06 Northrop Grumman Systems Corporation Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop
US10804913B1 (en) 2018-09-10 2020-10-13 Inphi Corporation Clock and data recovery devices with fractional-N PLL
US11303283B2 (en) 2020-01-13 2022-04-12 Artilux, Inc. Clock and data recovery circuitry with asymmetrical charge pump
CN113839671B (zh) * 2020-06-24 2026-02-03 中兴通讯股份有限公司 时钟发送装置及方法、时钟接收装置及方法
US11245406B2 (en) * 2020-06-30 2022-02-08 Silicon Laboratories Inc. Method for generation of independent clock signals from the same oscillator
DE112022001519T5 (de) * 2021-03-16 2024-01-11 Tektronix, Inc. Rauschkompensiertes jitter-messinstrument und verfahren
US12546809B2 (en) 2021-11-29 2026-02-10 Stmicroelectronics International N.V. Clock phase noise measurement circuit and method
CN120710500B (zh) * 2025-08-25 2025-11-07 上海晟联科半导体有限公司 控制字数字调整电路及基于小数n分频锁相环的重定时器
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Also Published As

Publication number Publication date
US7512203B2 (en) 2009-03-31
WO2006104808A1 (en) 2006-10-05
EP1867092A1 (de) 2007-12-19
JP2008535387A (ja) 2008-08-28
US20060222134A1 (en) 2006-10-05
CN101151838B (zh) 2013-03-27
TW200640146A (en) 2006-11-16
CN101151838A (zh) 2008-03-26
EP1867092B1 (de) 2011-11-23

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