ATE535074T1 - Verfahren und vorrichtung für intelligentes sortieren und prozessbestmmung von datenpaketen, die für eine zentrale verarbeitungseinheit eines routers oder servers aus einem datenpaketnetzwerk bestimmt sind - Google Patents

Verfahren und vorrichtung für intelligentes sortieren und prozessbestmmung von datenpaketen, die für eine zentrale verarbeitungseinheit eines routers oder servers aus einem datenpaketnetzwerk bestimmt sind

Info

Publication number
ATE535074T1
ATE535074T1 AT02757298T AT02757298T ATE535074T1 AT E535074 T1 ATE535074 T1 AT E535074T1 AT 02757298 T AT02757298 T AT 02757298T AT 02757298 T AT02757298 T AT 02757298T AT E535074 T1 ATE535074 T1 AT E535074T1
Authority
AT
Austria
Prior art keywords
packets
router
server
cpu
packet network
Prior art date
Application number
AT02757298T
Other languages
English (en)
Inventor
Russell Tuck
Puneet Agarwal
Original Assignee
Pluris Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25467122&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE535074(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Pluris Inc filed Critical Pluris Inc
Application granted granted Critical
Publication of ATE535074T1 publication Critical patent/ATE535074T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/6215—Individual queue per QOS, rate or priority
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2425—Traffic characterised by specific attributes, e.g. priority or QoS for supporting services specification, e.g. SLA
    • H04L47/2433—Allocation of priorities to traffic types
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2441—Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AT02757298T 2001-08-22 2002-08-21 Verfahren und vorrichtung für intelligentes sortieren und prozessbestmmung von datenpaketen, die für eine zentrale verarbeitungseinheit eines routers oder servers aus einem datenpaketnetzwerk bestimmt sind ATE535074T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/935,433 US6738378B2 (en) 2001-08-22 2001-08-22 Method and apparatus for intelligent sorting and process determination of data packets destined to a central processing unit of a router or server on a data packet network
PCT/US2002/026705 WO2003019868A1 (en) 2001-08-22 2002-08-21 Method and apparatus for intelligent sorting and process determination of data packets destined to a central processing unit of a router or server on a data packet network

Publications (1)

Publication Number Publication Date
ATE535074T1 true ATE535074T1 (de) 2011-12-15

Family

ID=25467122

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02757298T ATE535074T1 (de) 2001-08-22 2002-08-21 Verfahren und vorrichtung für intelligentes sortieren und prozessbestmmung von datenpaketen, die für eine zentrale verarbeitungseinheit eines routers oder servers aus einem datenpaketnetzwerk bestimmt sind

Country Status (4)

Country Link
US (2) US6738378B2 (de)
EP (1) EP1419618B1 (de)
AT (1) ATE535074T1 (de)
WO (1) WO2003019868A1 (de)

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US7076630B2 (en) 2000-02-08 2006-07-11 Mips Tech Inc Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
US7032226B1 (en) 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7155516B2 (en) * 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7502876B1 (en) 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7165257B2 (en) * 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7082552B2 (en) * 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
US7058064B2 (en) * 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US7042887B2 (en) 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7065096B2 (en) * 2000-06-23 2006-06-20 Mips Technologies, Inc. Method for allocating memory space for limited packet head and/or tail growth
US7649901B2 (en) * 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US7139901B2 (en) * 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US6738378B2 (en) * 2001-08-22 2004-05-18 Pluris, Inc. Method and apparatus for intelligent sorting and process determination of data packets destined to a central processing unit of a router or server on a data packet network
US7222148B2 (en) * 2002-05-02 2007-05-22 Bea Systems, Inc. System and method for providing highly available processing of asynchronous service requests
US7254639B1 (en) * 2002-05-20 2007-08-07 Cisco Technology, Inc. Methods and apparatus for directing packets among a group of processors
US7752629B2 (en) * 2004-05-21 2010-07-06 Bea Systems Inc. System and method for application server with overload protection
GB0413482D0 (en) * 2004-06-16 2004-07-21 Nokia Corp Packet queuing system and method
KR100460009B1 (ko) * 2004-06-23 2004-12-04 엔에이치엔(주) 이미지 리소스를 로딩하는 방법 및 이미지 리소스 로딩시스템
US20050286526A1 (en) * 2004-06-25 2005-12-29 Sood Sanjeev H Optimized algorithm for stream re-assembly
US7461173B2 (en) * 2004-06-30 2008-12-02 Intel Corporation Distributing timers across processors
US20060004933A1 (en) * 2004-06-30 2006-01-05 Sujoy Sen Network interface controller signaling of connection event
US20060031474A1 (en) * 2004-07-19 2006-02-09 Linden Cornett Maintaining reachability measures
US7542467B2 (en) * 2005-03-28 2009-06-02 Intel Corporation Out-of-band platform switch
US20060233174A1 (en) * 2005-03-28 2006-10-19 Rothman Michael A Method and apparatus for distributing switch/router capability across heterogeneous compute groups
US8037474B2 (en) * 2005-09-27 2011-10-11 Sony Computer Entertainment Inc. Task manager with stored task definition having pointer to a memory address containing required code data related to the task for execution
US7734827B2 (en) * 2005-09-27 2010-06-08 Sony Computer Entertainment, Inc. Operation of cell processors
US8141076B2 (en) * 2005-09-27 2012-03-20 Sony Computer Entertainment Inc. Cell processor methods and apparatus
US7975269B2 (en) * 2005-09-27 2011-07-05 Sony Computer Entertainment Inc. Parallel processor methods and apparatus
CN101150562B (zh) * 2007-10-29 2010-12-01 中兴通讯股份有限公司 一种降低cpu处理负荷的媒体流数据处理方法
US9178842B2 (en) 2008-11-05 2015-11-03 Commvault Systems, Inc. Systems and methods for monitoring messaging applications for compliance with a policy
US8345688B2 (en) * 2010-02-23 2013-01-01 Google Inc. System and method for managing flow of packets
DE102010020446B4 (de) 2010-05-12 2012-12-06 Wago Verwaltungsgesellschaft Mbh Automatisierungsgerät und Verfahren zur beschleunigten Verarbeitung von selektierten Prozessdaten
US20150261721A1 (en) * 2014-03-13 2015-09-17 Lantiq Deutschland Gmbh Flow control between processing devices
US10362149B2 (en) * 2016-12-30 2019-07-23 Intel Corporation Intelligent packet aggregation

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US6738378B2 (en) * 2001-08-22 2004-05-18 Pluris, Inc. Method and apparatus for intelligent sorting and process determination of data packets destined to a central processing unit of a router or server on a data packet network
US7242690B2 (en) * 2002-03-05 2007-07-10 Hewlett-Packard Development Company, L.P. System for performing input processing on a data packet

Also Published As

Publication number Publication date
EP1419618A4 (de) 2006-10-25
US7103046B2 (en) 2006-09-05
US20030039258A1 (en) 2003-02-27
WO2003019868A1 (en) 2003-03-06
US6738378B2 (en) 2004-05-18
EP1419618B1 (de) 2011-11-23
EP1419618A1 (de) 2004-05-19
US20040208178A1 (en) 2004-10-21

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