ATE538535T1 - Digitale frequenzgeregelte verzögerungsleitung - Google Patents

Digitale frequenzgeregelte verzögerungsleitung

Info

Publication number
ATE538535T1
ATE538535T1 AT05783789T AT05783789T ATE538535T1 AT E538535 T1 ATE538535 T1 AT E538535T1 AT 05783789 T AT05783789 T AT 05783789T AT 05783789 T AT05783789 T AT 05783789T AT E538535 T1 ATE538535 T1 AT E538535T1
Authority
AT
Austria
Prior art keywords
delay line
signal
digital frequency
controlled delay
frequency controlled
Prior art date
Application number
AT05783789T
Other languages
English (en)
Inventor
Curt Schnarr
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE538535T1 publication Critical patent/ATE538535T1/de

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)
AT05783789T 2004-08-05 2005-08-05 Digitale frequenzgeregelte verzögerungsleitung ATE538535T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/912,441 US7664216B2 (en) 2004-08-05 2004-08-05 Digital frequency locked delay line
PCT/US2005/027863 WO2006017723A1 (en) 2004-08-05 2005-08-05 Digital frequency locked delay line

Publications (1)

Publication Number Publication Date
ATE538535T1 true ATE538535T1 (de) 2012-01-15

Family

ID=35335195

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05783789T ATE538535T1 (de) 2004-08-05 2005-08-05 Digitale frequenzgeregelte verzögerungsleitung

Country Status (7)

Country Link
US (3) US7664216B2 (de)
EP (1) EP1779517B1 (de)
JP (1) JP2008509609A (de)
CN (1) CN101002390B (de)
AT (1) ATE538535T1 (de)
TW (1) TWI330947B (de)
WO (1) WO2006017723A1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6996817B2 (en) * 2001-12-12 2006-02-07 Valve Corporation Method and system for upgrading and rolling back versions
US7664216B2 (en) 2004-08-05 2010-02-16 Micron Technology, Inc. Digital frequency locked delay line
US7221202B1 (en) * 2004-09-15 2007-05-22 Cypress Semiconductor Corporation Delay-locked loop with reduced susceptibility to false lock
TWI256539B (en) * 2004-11-09 2006-06-11 Realtek Semiconductor Corp Apparatus and method for generating a clock signal
JP4106383B2 (ja) * 2006-06-08 2008-06-25 インターナショナル・ビジネス・マシーンズ・コーポレーション 遅延比率調整回路、遅延パルス生成回路及びパルス幅変調パルス信号発生装置。
KR100818729B1 (ko) 2006-07-31 2008-04-01 삼성전자주식회사 지연 동기 루프 회로 및 클럭 신호 발생 방법
US7746134B1 (en) * 2007-04-18 2010-06-29 Altera Corporation Digitally controlled delay-locked loops
US7586799B2 (en) * 2007-09-27 2009-09-08 Micron Technology, Inc. Devices, systems, and methods for independent output drive strengths
JP5458556B2 (ja) * 2008-11-27 2014-04-02 ソニー株式会社 タイミング調整回路、固体撮像素子、およびカメラシステム
JP2010200090A (ja) * 2009-02-26 2010-09-09 Toshiba Corp 位相補償用クロック同期回路
KR101062743B1 (ko) * 2009-04-15 2011-09-06 주식회사 하이닉스반도체 반도체 집적 회로 및 그 제어 방법
US8054101B2 (en) * 2009-05-07 2011-11-08 Faraday Technology Corp. Current source applicable to a controllable delay line and design method thereof
US8120432B2 (en) * 2009-06-19 2012-02-21 Rockstar Bidco, LP System and method for selecting optimum local oscillator discipline source
JP2013021396A (ja) * 2011-07-07 2013-01-31 Elpida Memory Inc 半導体装置及びその制御方法
KR101830713B1 (ko) * 2011-07-08 2018-02-22 한국전자통신연구원 코드 주기를 이용한 신호 처리 방법 및 상관기, 소프트웨어 신호 수신기
US20130200937A1 (en) * 2012-02-07 2013-08-08 International Business Machines Corporation Delay line with cell by cell power down capability
EP2660782B1 (de) 2012-05-02 2019-04-10 Dassault Systèmes Design eines 3D-modellierten Objekts
TWI489286B (zh) * 2012-07-13 2015-06-21 Via Tech Inc 集線器裝置以及用以初始化集線器裝置的方法
CN103383676B (zh) 2012-07-13 2016-07-20 威盛电子股份有限公司 集线器装置以及用以初始化集线器装置的方法
KR102041471B1 (ko) * 2012-12-24 2019-11-07 에스케이하이닉스 주식회사 반도체 장치
US8963646B1 (en) * 2013-08-19 2015-02-24 Nanya Technology Corporation Delay line ring oscillation apparatus
US9419598B2 (en) * 2013-11-26 2016-08-16 Rambus Inc. In-situ delay element calibration
CN103888132A (zh) * 2014-04-02 2014-06-25 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种产生i/q两路正交时钟的电路及方法
CN104333369B (zh) * 2014-07-08 2017-08-29 北京芯诣世纪科技有限公司 一种ddr3 phy sstl15输出驱动电路
US9866221B2 (en) * 2016-05-24 2018-01-09 International Business Machines Corporation Test circuit to isolate HCI degradation
KR102521756B1 (ko) * 2016-06-22 2023-04-14 삼성전자주식회사 반도체 메모리 장치의 지연 회로, 반도체 메모리 장치 및 이의 동작 방법
JP2022127330A (ja) * 2021-02-19 2022-08-31 キオクシア株式会社 半導体集積回路
KR20230165455A (ko) 2022-05-27 2023-12-05 삼성전자주식회사 딜레이 제어 회로 및 그를 포함하는 메모리 모듈

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4792768A (en) 1987-11-06 1988-12-20 Hewlett-Packard Company Fast frequency settling signal generator utilizing a frequency locked-loop
US4890071A (en) 1988-10-26 1989-12-26 Hewlett-Packard Company Signal generator utilizing a combined phase locked and frequency locked loop
US4918405A (en) 1988-10-26 1990-04-17 Hewlett-Packard Company Signal generator utilizing a combined phase locked and frequency locked loop
US5252867A (en) 1992-02-14 1993-10-12 Vlsi Technology, Inc. Self-compensating digital delay semiconductor device with selectable output delays and method therefor
JP2573787B2 (ja) * 1993-05-18 1997-01-22 株式会社メガチップス パルス幅変調回路
FR2710800B1 (fr) 1993-09-27 1995-12-15 Sgs Thomson Microelectronics Ligne à retard numérique.
JP3169794B2 (ja) 1995-05-26 2001-05-28 日本電気株式会社 遅延クロック生成回路
JP3431053B2 (ja) * 1996-09-17 2003-07-28 株式会社アドバンテスト タイミング発生装置
US5990714A (en) 1996-12-26 1999-11-23 United Microelectronics Corporation Clock signal generating circuit using variable delay circuit
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
JP3789598B2 (ja) * 1997-05-20 2006-06-28 富士通株式会社 複数種類のスキューを低減する回路及び半導体装置
JP3708285B2 (ja) * 1997-05-16 2005-10-19 富士通株式会社 スキュー低減回路と半導体装置
JP3708284B2 (ja) * 1997-05-16 2005-10-19 富士通株式会社 スキュー低減回路と半導体装置
JP3727753B2 (ja) * 1997-05-16 2005-12-14 富士通株式会社 スキュー低減回路と半導体装置
US6114890A (en) 1997-05-16 2000-09-05 Fujitsu Limited Skew-reduction circuit
TW383486B (en) 1997-09-17 2000-03-01 Powerchip Semiconductor Corp Phase detector and digital delay line applied to delay lock loop
US6160860A (en) 1998-01-28 2000-12-12 Lucent Technologies Inc. Phase-locked loop (PLL) circuit containing a frequency detector for improved frequency acquisition
US6137325A (en) 1998-06-22 2000-10-24 Micron Technology, Inc. Device and methods in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
US6777995B1 (en) 1999-02-26 2004-08-17 Micron Technology, Inc. Interlaced delay-locked loops for controlling memory-circuit timing
US6326826B1 (en) 1999-05-27 2001-12-04 Silicon Image, Inc. Wide frequency-range delay-locked loop circuit
US6388480B1 (en) 1999-08-30 2002-05-14 Micron Technology, Inc. Method and apparatus for reducing the lock time of DLL
US6242955B1 (en) 1999-09-20 2001-06-05 Silicon Magic Corporation Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal
US6356158B1 (en) 2000-05-02 2002-03-12 Xilinx, Inc. Phase-locked loop employing programmable tapped-delay-line oscillator
US6445231B1 (en) 2000-06-01 2002-09-03 Micron Technology, Inc. Digital dual-loop DLL design using coarse and fine loops
JP3968963B2 (ja) 2000-06-30 2007-08-29 コニカミノルタホールディングス株式会社 ディジタルpllパルス発生装置
JP3823697B2 (ja) * 2000-07-11 2006-09-20 富士通株式会社 同期パターン位置検出回路
US6636093B1 (en) 2000-07-14 2003-10-21 Micron Technology, Inc. Compensation for a delay locked loop
JP3807593B2 (ja) 2000-07-24 2006-08-09 株式会社ルネサステクノロジ クロック生成回路および制御方法並びに半導体記憶装置
US6868504B1 (en) 2000-08-31 2005-03-15 Micron Technology, Inc. Interleaved delay line for phase locked and delay locked loops
JP3619466B2 (ja) * 2001-03-27 2005-02-09 松下電器産業株式会社 半導体装置
US6839860B2 (en) 2001-04-19 2005-01-04 Mircon Technology, Inc. Capture clock generator using master and slave delay locked loops
US6901013B2 (en) 2001-06-05 2005-05-31 Micron Technology, Inc. Controller for delay locked loop circuits
US7245540B2 (en) 2001-06-05 2007-07-17 Micron Technology, Inc. Controller for delay locked loop circuits
US6876239B2 (en) 2001-07-11 2005-04-05 Micron Technology, Inc. Delay locked loop “ACTIVE command” reactor
US7072433B2 (en) * 2001-07-11 2006-07-04 Micron Technology, Inc. Delay locked loop fine tune
US6798259B2 (en) 2001-08-03 2004-09-28 Micron Technology, Inc. System and method to improve the efficiency of synchronous mirror delays and delay locked loops
US6556489B2 (en) 2001-08-06 2003-04-29 Micron Technology, Inc. Method and apparatus for determining digital delay line entry point
US6850107B2 (en) 2001-08-29 2005-02-01 Micron Technology, Inc. Variable delay circuit and method, and delay locked loop, memory device and computer system using same
US6605969B2 (en) 2001-10-09 2003-08-12 Micron Technology, Inc. Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers
US6759911B2 (en) 2001-11-19 2004-07-06 Mcron Technology, Inc. Delay-locked loop circuit and method using a ring oscillator and counter-based delay
US6774687B2 (en) 2002-03-11 2004-08-10 Micron Technology, Inc. Method and apparatus for characterizing a delay locked loop
KR100454129B1 (ko) 2002-05-06 2004-10-26 삼성전자주식회사 코드 변환 장치, 디지털-아날로그 변환 장치, 그리고 지연동기 루프회로
US7319728B2 (en) * 2002-05-16 2008-01-15 Micron Technology, Inc. Delay locked loop with frequency control
US6809990B2 (en) 2002-06-21 2004-10-26 Micron Technology, Inc. Delay locked loop control circuit
US6680874B1 (en) 2002-08-29 2004-01-20 Micron Technology, Inc. Delay lock loop circuit useful in a synchronous system and associated methods
US7028206B2 (en) * 2002-12-16 2006-04-11 William Kenneth Waller Circuit and method for generating a local clock signal synchronized to an externally generated reference clock signal
US6839301B2 (en) 2003-04-28 2005-01-04 Micron Technology, Inc. Method and apparatus for improving stability and lock time for synchronous circuits
US20040222832A1 (en) * 2003-05-09 2004-11-11 Chaiyuth Chansungsan Interpolator circuit
US6937076B2 (en) * 2003-06-11 2005-08-30 Micron Technology, Inc. Clock synchronizing apparatus and method using frequency dependent variable delay
KR100605604B1 (ko) * 2003-10-29 2006-07-28 주식회사 하이닉스반도체 지연 고정 루프 및 그 제어 방법
US7694202B2 (en) * 2004-01-28 2010-04-06 Micron Technology, Inc. Providing memory test patterns for DLL calibration
US7444559B2 (en) * 2004-01-28 2008-10-28 Micron Technology, Inc. Generation of memory test patterns for DLL calibration
RU2346996C2 (ru) 2004-06-29 2009-02-20 ЮРОПИЭН НИКЕЛЬ ПиЭлСи Усовершенствованное выщелачивание основных металлов
US7109768B2 (en) * 2004-06-29 2006-09-19 Intel Corporation Closed-loop control of driver slew rate
US7664216B2 (en) 2004-08-05 2010-02-16 Micron Technology, Inc. Digital frequency locked delay line
US7977994B2 (en) * 2007-06-15 2011-07-12 The Regents Of The University Of Colorado, A Body Corporate Digital pulse-width-modulator with discretely adjustable delay line

Also Published As

Publication number Publication date
US20060029175A1 (en) 2006-02-09
CN101002390A (zh) 2007-07-18
EP1779517B1 (de) 2011-12-21
US7664216B2 (en) 2010-02-16
US20100142660A1 (en) 2010-06-10
US20120063551A1 (en) 2012-03-15
US8437428B2 (en) 2013-05-07
JP2008509609A (ja) 2008-03-27
EP1779517A1 (de) 2007-05-02
TW200620839A (en) 2006-06-16
WO2006017723A1 (en) 2006-02-16
US8064562B2 (en) 2011-11-22
TWI330947B (en) 2010-09-21
CN101002390B (zh) 2012-08-29

Similar Documents

Publication Publication Date Title
ATE538535T1 (de) Digitale frequenzgeregelte verzögerungsleitung
DE602005013565D1 (de) Zwei-bit-a-/d-wandler mit versatzlöschung, verbesserter gleichtaktunterdrückung und schwellensensitivität
WO2009140538A3 (en) Systems for combining inputs from electronic musical instruments and devices
TW200709573A (en) A semiconductor device, spread spectrum clock generator and method thereof
DE602007013023D1 (de) Testzugangsportschalter
TW200801891A (en) Dynamic timing adjustment in a circuit device
WO2008005347A3 (en) Auto-gain switching module for acoustic touch systems
WO2010057037A3 (en) Lo generation with deskewed input oscillator signal and single ended dynamic divider for differential quadrature signals
ATE465424T1 (de) Bestimmung der flugzeit eines signals
TW200700755A (en) System and scanout circuits with error resilience circuit
TW200513824A (en) Synchronizer apparatus for synchronizing data from one clock domain to another clock domain
TW200633393A (en) Semiconductor device and electronic apparatus using the same
TW200746018A (en) Display device and electronic device having the same
JP2017028489A (ja) スキュー補正回路、電子装置及びスキュー補正方法
TW200721692A (en) Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by a frequency synthesizer
DE60314301D1 (de) Frequenzvervielfacher
TW200700758A (en) Delay circuit, test circuit, timing generation device, test module, and electronic device
TW200743930A (en) Adjusting circuit for delay circuit
WO2007146599A3 (en) Integer represenation of relative timing between desired output samples and corresponding input samples
ATE532267T1 (de) Verzögerungsregelschleife
ATE400160T1 (de) Hörvorrichtung mit orthogonal zueinander angeordneten spulen
TW200620319A (en) Apparatus for driving output signals from DLL circult
DE60224796D1 (de) Verfahren zur inversen filterung, verfahren zur synthesefilterung, entsprechende filterungsvorrichtungen und vorrichtungen mit solchen filterungsvorrichtungen
WO2010017977A3 (en) Simultaneous bi-directional data transfer
WO2004053927A3 (en) Simultaneous bidirectional differential signalling interface