ATE538535T1 - Digitale frequenzgeregelte verzögerungsleitung - Google Patents
Digitale frequenzgeregelte verzögerungsleitungInfo
- Publication number
- ATE538535T1 ATE538535T1 AT05783789T AT05783789T ATE538535T1 AT E538535 T1 ATE538535 T1 AT E538535T1 AT 05783789 T AT05783789 T AT 05783789T AT 05783789 T AT05783789 T AT 05783789T AT E538535 T1 ATE538535 T1 AT E538535T1
- Authority
- AT
- Austria
- Prior art keywords
- delay line
- signal
- digital frequency
- controlled delay
- frequency controlled
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
Landscapes
- Dram (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transceivers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/912,441 US7664216B2 (en) | 2004-08-05 | 2004-08-05 | Digital frequency locked delay line |
| PCT/US2005/027863 WO2006017723A1 (en) | 2004-08-05 | 2005-08-05 | Digital frequency locked delay line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE538535T1 true ATE538535T1 (de) | 2012-01-15 |
Family
ID=35335195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05783789T ATE538535T1 (de) | 2004-08-05 | 2005-08-05 | Digitale frequenzgeregelte verzögerungsleitung |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US7664216B2 (de) |
| EP (1) | EP1779517B1 (de) |
| JP (1) | JP2008509609A (de) |
| CN (1) | CN101002390B (de) |
| AT (1) | ATE538535T1 (de) |
| TW (1) | TWI330947B (de) |
| WO (1) | WO2006017723A1 (de) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6996817B2 (en) * | 2001-12-12 | 2006-02-07 | Valve Corporation | Method and system for upgrading and rolling back versions |
| US7664216B2 (en) | 2004-08-05 | 2010-02-16 | Micron Technology, Inc. | Digital frequency locked delay line |
| US7221202B1 (en) * | 2004-09-15 | 2007-05-22 | Cypress Semiconductor Corporation | Delay-locked loop with reduced susceptibility to false lock |
| TWI256539B (en) * | 2004-11-09 | 2006-06-11 | Realtek Semiconductor Corp | Apparatus and method for generating a clock signal |
| JP4106383B2 (ja) * | 2006-06-08 | 2008-06-25 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 遅延比率調整回路、遅延パルス生成回路及びパルス幅変調パルス信号発生装置。 |
| KR100818729B1 (ko) | 2006-07-31 | 2008-04-01 | 삼성전자주식회사 | 지연 동기 루프 회로 및 클럭 신호 발생 방법 |
| US7746134B1 (en) * | 2007-04-18 | 2010-06-29 | Altera Corporation | Digitally controlled delay-locked loops |
| US7586799B2 (en) * | 2007-09-27 | 2009-09-08 | Micron Technology, Inc. | Devices, systems, and methods for independent output drive strengths |
| JP5458556B2 (ja) * | 2008-11-27 | 2014-04-02 | ソニー株式会社 | タイミング調整回路、固体撮像素子、およびカメラシステム |
| JP2010200090A (ja) * | 2009-02-26 | 2010-09-09 | Toshiba Corp | 位相補償用クロック同期回路 |
| KR101062743B1 (ko) * | 2009-04-15 | 2011-09-06 | 주식회사 하이닉스반도체 | 반도체 집적 회로 및 그 제어 방법 |
| US8054101B2 (en) * | 2009-05-07 | 2011-11-08 | Faraday Technology Corp. | Current source applicable to a controllable delay line and design method thereof |
| US8120432B2 (en) * | 2009-06-19 | 2012-02-21 | Rockstar Bidco, LP | System and method for selecting optimum local oscillator discipline source |
| JP2013021396A (ja) * | 2011-07-07 | 2013-01-31 | Elpida Memory Inc | 半導体装置及びその制御方法 |
| KR101830713B1 (ko) * | 2011-07-08 | 2018-02-22 | 한국전자통신연구원 | 코드 주기를 이용한 신호 처리 방법 및 상관기, 소프트웨어 신호 수신기 |
| US20130200937A1 (en) * | 2012-02-07 | 2013-08-08 | International Business Machines Corporation | Delay line with cell by cell power down capability |
| EP2660782B1 (de) | 2012-05-02 | 2019-04-10 | Dassault Systèmes | Design eines 3D-modellierten Objekts |
| TWI489286B (zh) * | 2012-07-13 | 2015-06-21 | Via Tech Inc | 集線器裝置以及用以初始化集線器裝置的方法 |
| CN103383676B (zh) | 2012-07-13 | 2016-07-20 | 威盛电子股份有限公司 | 集线器装置以及用以初始化集线器装置的方法 |
| KR102041471B1 (ko) * | 2012-12-24 | 2019-11-07 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| US8963646B1 (en) * | 2013-08-19 | 2015-02-24 | Nanya Technology Corporation | Delay line ring oscillation apparatus |
| US9419598B2 (en) * | 2013-11-26 | 2016-08-16 | Rambus Inc. | In-situ delay element calibration |
| CN103888132A (zh) * | 2014-04-02 | 2014-06-25 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | 一种产生i/q两路正交时钟的电路及方法 |
| CN104333369B (zh) * | 2014-07-08 | 2017-08-29 | 北京芯诣世纪科技有限公司 | 一种ddr3 phy sstl15输出驱动电路 |
| US9866221B2 (en) * | 2016-05-24 | 2018-01-09 | International Business Machines Corporation | Test circuit to isolate HCI degradation |
| KR102521756B1 (ko) * | 2016-06-22 | 2023-04-14 | 삼성전자주식회사 | 반도체 메모리 장치의 지연 회로, 반도체 메모리 장치 및 이의 동작 방법 |
| JP2022127330A (ja) * | 2021-02-19 | 2022-08-31 | キオクシア株式会社 | 半導体集積回路 |
| KR20230165455A (ko) | 2022-05-27 | 2023-12-05 | 삼성전자주식회사 | 딜레이 제어 회로 및 그를 포함하는 메모리 모듈 |
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| US4890071A (en) | 1988-10-26 | 1989-12-26 | Hewlett-Packard Company | Signal generator utilizing a combined phase locked and frequency locked loop |
| US4918405A (en) | 1988-10-26 | 1990-04-17 | Hewlett-Packard Company | Signal generator utilizing a combined phase locked and frequency locked loop |
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| JP2573787B2 (ja) * | 1993-05-18 | 1997-01-22 | 株式会社メガチップス | パルス幅変調回路 |
| FR2710800B1 (fr) | 1993-09-27 | 1995-12-15 | Sgs Thomson Microelectronics | Ligne à retard numérique. |
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| US7977994B2 (en) * | 2007-06-15 | 2011-07-12 | The Regents Of The University Of Colorado, A Body Corporate | Digital pulse-width-modulator with discretely adjustable delay line |
-
2004
- 2004-08-05 US US10/912,441 patent/US7664216B2/en active Active
-
2005
- 2005-07-27 TW TW094125401A patent/TWI330947B/zh not_active IP Right Cessation
- 2005-08-05 CN CN2005800265317A patent/CN101002390B/zh not_active Expired - Lifetime
- 2005-08-05 JP JP2007525024A patent/JP2008509609A/ja active Pending
- 2005-08-05 AT AT05783789T patent/ATE538535T1/de active
- 2005-08-05 EP EP05783789A patent/EP1779517B1/de not_active Expired - Lifetime
- 2005-08-05 WO PCT/US2005/027863 patent/WO2006017723A1/en not_active Ceased
-
2010
- 2010-02-12 US US12/705,320 patent/US8064562B2/en not_active Expired - Lifetime
-
2011
- 2011-11-17 US US13/299,085 patent/US8437428B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20060029175A1 (en) | 2006-02-09 |
| CN101002390A (zh) | 2007-07-18 |
| EP1779517B1 (de) | 2011-12-21 |
| US7664216B2 (en) | 2010-02-16 |
| US20100142660A1 (en) | 2010-06-10 |
| US20120063551A1 (en) | 2012-03-15 |
| US8437428B2 (en) | 2013-05-07 |
| JP2008509609A (ja) | 2008-03-27 |
| EP1779517A1 (de) | 2007-05-02 |
| TW200620839A (en) | 2006-06-16 |
| WO2006017723A1 (en) | 2006-02-16 |
| US8064562B2 (en) | 2011-11-22 |
| TWI330947B (en) | 2010-09-21 |
| CN101002390B (zh) | 2012-08-29 |
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