ATE541312T1 - Chip mit zwei gruppen von chipkontakten - Google Patents

Chip mit zwei gruppen von chipkontakten

Info

Publication number
ATE541312T1
ATE541312T1 AT05747294T AT05747294T ATE541312T1 AT E541312 T1 ATE541312 T1 AT E541312T1 AT 05747294 T AT05747294 T AT 05747294T AT 05747294 T AT05747294 T AT 05747294T AT E541312 T1 ATE541312 T1 AT E541312T1
Authority
AT
Austria
Prior art keywords
chip
contacts
groups
passivating layer
conductor
Prior art date
Application number
AT05747294T
Other languages
English (en)
Inventor
Heimo Scheucher
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE541312T1 publication Critical patent/ATE541312T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/699—Insulating or insulated package substrates; Interposers; Redistribution layers for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT05747294T 2004-05-28 2005-05-18 Chip mit zwei gruppen von chipkontakten ATE541312T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04102408 2004-05-28
PCT/IB2005/051613 WO2005117109A1 (en) 2004-05-28 2005-05-18 Chip having two groups of chip contacts

Publications (1)

Publication Number Publication Date
ATE541312T1 true ATE541312T1 (de) 2012-01-15

Family

ID=34970726

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05747294T ATE541312T1 (de) 2004-05-28 2005-05-18 Chip mit zwei gruppen von chipkontakten

Country Status (7)

Country Link
US (1) US9318428B2 (de)
EP (1) EP1754256B1 (de)
JP (1) JP2008501231A (de)
KR (1) KR20070034530A (de)
CN (1) CN1961424B (de)
AT (1) ATE541312T1 (de)
WO (1) WO2005117109A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602008003128D1 (de) 2007-07-12 2010-12-02 Nxp Bv Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen
US20150129665A1 (en) * 2013-11-13 2015-05-14 David Finn Connection bridges for dual interface transponder chip modules
US11068770B2 (en) 2014-03-08 2021-07-20 Féinics AmaTech Teoranta Lower Churchfield Connection bridges for dual interface transponder chip modules
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
EP3423993B1 (de) * 2016-03-01 2020-07-01 Cardlab ApS Schaltungsschicht für eine chipkarte
KR102495071B1 (ko) 2016-03-02 2023-02-01 피에이. 코테 패밀리 홀딩 게엠베하 디스플레이 디바이스 제조 방법 및 디스플레이 디바이스

Family Cites Families (30)

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JPS63216994A (ja) 1987-03-06 1988-09-09 Fujitsu Ltd 段差メツキ方法
JPH0439950A (ja) 1990-06-05 1992-02-10 Alps Electric Co Ltd 半導体装置
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JPH04278542A (ja) 1991-03-06 1992-10-05 Fujitsu Ltd 半導体装置及びその製造方法
JP2509422B2 (ja) 1991-10-30 1996-06-19 三菱電機株式会社 半導体装置及びその製造方法
US5384487A (en) 1993-05-05 1995-01-24 Lsi Logic Corporation Off-axis power branches for interior bond pad arrangements
EP0819318B1 (de) * 1995-04-05 2003-05-14 Unitive International Limited Eine löthöckerstruktur für ein mikroelektronisches substrat
US5874782A (en) * 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
KR100239695B1 (ko) * 1996-09-11 2000-01-15 김영환 칩 사이즈 반도체 패키지 및 그 제조 방법
US6162724A (en) * 1996-09-12 2000-12-19 Mosel Vitelic Inc. Method for forming metalization for inter-layer connections
JP3022819B2 (ja) * 1997-08-27 2000-03-21 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置
JP3549714B2 (ja) 1997-09-11 2004-08-04 沖電気工業株式会社 半導体装置
US6441487B2 (en) 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
DE19808193B4 (de) * 1998-02-27 2007-11-08 Robert Bosch Gmbh Leadframevorrichtung und entsprechendes Herstellungsverfahren
US6373143B1 (en) * 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
US6232666B1 (en) * 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
JP4074721B2 (ja) 1999-02-23 2008-04-09 ローム株式会社 半導体チップおよび半導体チップの製造方法
US6707159B1 (en) * 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
US6400016B2 (en) * 2000-01-14 2002-06-04 I-Ming Chen Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate
DE10014300A1 (de) * 2000-03-23 2001-10-04 Infineon Technologies Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
DE10024376A1 (de) 2000-05-17 2001-12-06 Infineon Technologies Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
JP2002289768A (ja) * 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
TW494548B (en) * 2000-08-25 2002-07-11 I-Ming Chen Semiconductor chip device and its package method
DE10055001A1 (de) 2000-11-07 2002-05-16 Infineon Technologies Ag Speicheranordnung mit einem zentralen Anschlussfeld
US6359342B1 (en) * 2000-12-05 2002-03-19 Siliconware Precision Industries Co., Ltd. Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same
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US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
US6856022B2 (en) * 2003-03-31 2005-02-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device
FR2853434B1 (fr) * 2003-04-03 2005-07-01 Oberthur Card Syst Sa Carte a microcircuit fixee sur un support adaptateur, support de carte et procede de fabrication
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto

Also Published As

Publication number Publication date
KR20070034530A (ko) 2007-03-28
US20080017980A1 (en) 2008-01-24
WO2005117109A1 (en) 2005-12-08
JP2008501231A (ja) 2008-01-17
CN1961424A (zh) 2007-05-09
CN1961424B (zh) 2010-08-11
EP1754256A1 (de) 2007-02-21
EP1754256B1 (de) 2012-01-11
US9318428B2 (en) 2016-04-19

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