ATE542180T1 - Effiziente interrupt-nachrichtendefinition - Google Patents

Effiziente interrupt-nachrichtendefinition

Info

Publication number
ATE542180T1
ATE542180T1 AT08861057T AT08861057T ATE542180T1 AT E542180 T1 ATE542180 T1 AT E542180T1 AT 08861057 T AT08861057 T AT 08861057T AT 08861057 T AT08861057 T AT 08861057T AT E542180 T1 ATE542180 T1 AT E542180T1
Authority
AT
Austria
Prior art keywords
processors
processor
interrupt
messages
computer
Prior art date
Application number
AT08861057T
Other languages
English (en)
Inventor
Bruce Worthington
Vinod Mamtani
Brian Railing
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Application granted granted Critical
Publication of ATE542180T1 publication Critical patent/ATE542180T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
AT08861057T 2007-12-17 2008-11-25 Effiziente interrupt-nachrichtendefinition ATE542180T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/002,442 US7783811B2 (en) 2007-12-17 2007-12-17 Efficient interrupt message definition
PCT/US2008/084622 WO2009079172A1 (en) 2007-12-17 2008-11-25 Efficient interrupt message definition

Publications (1)

Publication Number Publication Date
ATE542180T1 true ATE542180T1 (de) 2012-02-15

Family

ID=40754769

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08861057T ATE542180T1 (de) 2007-12-17 2008-11-25 Effiziente interrupt-nachrichtendefinition

Country Status (5)

Country Link
US (1) US7783811B2 (de)
EP (1) EP2225650B1 (de)
CN (1) CN101896896B (de)
AT (1) ATE542180T1 (de)
WO (1) WO2009079172A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
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US7805556B2 (en) * 2007-05-01 2010-09-28 Ricoh Company, Ltd. Interrupt control apparatus, bus bridge, bus switch, image processing apparatus, and interrupt control method
CN101546276B (zh) * 2008-03-26 2012-12-19 国际商业机器公司 多核环境下实现中断调度的方法及多核处理器
US8024504B2 (en) * 2008-06-26 2011-09-20 Microsoft Corporation Processor interrupt determination
US20090327556A1 (en) * 2008-06-27 2009-12-31 Microsoft Corporation Processor Interrupt Selection
US8527988B1 (en) * 2009-07-31 2013-09-03 Hewlett-Packard Development Company, L.P. Proximity mapping of virtual-machine threads to processors
US8473723B2 (en) * 2009-12-10 2013-06-25 International Business Machines Corporation Computer program product for managing processing resources
US8869171B2 (en) * 2010-12-23 2014-10-21 Mellanox Technologies Ltd. Low-latency communications
US10114662B2 (en) * 2013-02-26 2018-10-30 Red Hat Israel, Ltd. Updating processor topology information for virtual machines
US10061622B2 (en) 2013-02-26 2018-08-28 Red Hat Israel, Ltd. Updating memory topology information for virtual machines
KR101583325B1 (ko) * 2014-08-12 2016-01-07 주식회사 구버넷 가상 패킷을 처리하는 네트워크 인터페이스 장치 및 그 방법
GB2538754B (en) * 2015-05-27 2018-08-29 Displaylink Uk Ltd Single-chip multi-processor communication
US11210246B2 (en) * 2018-08-24 2021-12-28 Advanced Micro Devices, Inc. Probe interrupt delivery
US20230289212A1 (en) * 2022-03-10 2023-09-14 Nvidia Corporation Flexible Migration of Executing Software Between Processing Components Without Need For Hardware Reset

Family Cites Families (21)

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Publication number Priority date Publication date Assignee Title
KR0145925B1 (ko) 1995-01-27 1998-09-15 박성규 컴퓨터 분야의 인터럽트 제어 장치
US6253275B1 (en) * 1998-11-25 2001-06-26 Advanced Micro Devices, Inc. Interrupt gating method for PCI bridges
US6983339B1 (en) * 2000-09-29 2006-01-03 Intel Corporation Method and apparatus for processing interrupts of a bus
US6772241B1 (en) * 2000-09-29 2004-08-03 Intel Corporation Selective interrupt delivery to multiple processors having independent operating systems
US6738847B1 (en) * 2000-11-10 2004-05-18 Unisys Corporation Method for assigning a multiplicity of interrupt vectors in a symmetric multi-processor computing environment
US7328294B2 (en) * 2001-12-03 2008-02-05 Sun Microsystems, Inc. Methods and apparatus for distributing interrupts
US7529875B2 (en) * 2003-08-20 2009-05-05 International Business Machines Corporation Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system
US7117285B2 (en) * 2003-08-29 2006-10-03 Sun Microsystems, Inc. Method and system for efficiently directing interrupts
US7363407B2 (en) * 2003-09-29 2008-04-22 Microsoft Corporation Concurrent arbitration of multidimensional requests for interrupt resources
US7222203B2 (en) 2003-12-08 2007-05-22 Intel Corporation Interrupt redirection for virtual partitioning
US7197588B2 (en) * 2004-03-31 2007-03-27 Intel Corporation Interrupt scheme for an Input/Output device
US7496706B2 (en) * 2004-06-30 2009-02-24 Intel Corporation Message signaled interrupt redirection table
DE102004042170B4 (de) * 2004-08-31 2009-02-19 Advanced Micro Devices, Inc., Sunnyvale Nachrichtenbasierte Interrupttabelle
US20060112208A1 (en) * 2004-11-22 2006-05-25 International Business Machines Corporation Interrupt thresholding for SMT and multi processor systems
US20060259733A1 (en) 2005-05-13 2006-11-16 Sony Computer Entertainment Inc. Methods and apparatus for resource management in a logically partitioned processing environment
US20060294277A1 (en) * 2005-06-24 2006-12-28 Tetrick Raymond S Message signaled interrupt redirection
US20070005742A1 (en) * 2005-06-30 2007-01-04 Avigdor Eldar Efficient network communications via directed processor interrupts
TW200708969A (en) 2005-08-24 2007-03-01 Tyan Computer Corp ID allocating method for advanced programmable interrupt controller
US7769938B2 (en) * 2007-09-06 2010-08-03 Intel Corporation Processor selection for an interrupt identifying a processor cluster
US8032681B2 (en) * 2007-09-06 2011-10-04 Intel Corporation Processor selection for an interrupt based on willingness to accept the interrupt and on priority
US7962679B2 (en) * 2007-09-28 2011-06-14 Intel Corporation Interrupt balancing for multi-core and power

Also Published As

Publication number Publication date
US20090157935A1 (en) 2009-06-18
CN101896896B (zh) 2013-08-21
WO2009079172A1 (en) 2009-06-25
EP2225650A4 (de) 2011-01-12
CN101896896A (zh) 2010-11-24
EP2225650A1 (de) 2010-09-08
EP2225650B1 (de) 2012-01-18
US7783811B2 (en) 2010-08-24

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