ATE545151T1 - Verfahren zum binden zweier aus materialien, die aus halbleitermaterialien ausgewählt wurden, hergestellter wafer - Google Patents

Verfahren zum binden zweier aus materialien, die aus halbleitermaterialien ausgewählt wurden, hergestellter wafer

Info

Publication number
ATE545151T1
ATE545151T1 AT06743328T AT06743328T ATE545151T1 AT E545151 T1 ATE545151 T1 AT E545151T1 AT 06743328 T AT06743328 T AT 06743328T AT 06743328 T AT06743328 T AT 06743328T AT E545151 T1 ATE545151 T1 AT E545151T1
Authority
AT
Austria
Prior art keywords
plasma
activated
wafers
activation
bonding
Prior art date
Application number
AT06743328T
Other languages
English (en)
Inventor
Sebastien Kerdiles
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE545151T1 publication Critical patent/ATE545151T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Pressure Welding/Diffusion-Bonding (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Plasma Technology (AREA)
AT06743328T 2005-04-22 2006-04-18 Verfahren zum binden zweier aus materialien, die aus halbleitermaterialien ausgewählt wurden, hergestellter wafer ATE545151T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0504093A FR2884966B1 (fr) 2005-04-22 2005-04-22 Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
PCT/EP2006/061647 WO2006111533A1 (en) 2005-04-22 2006-04-18 A method of bonding two wafers made out of materials selected from semiconductor materials

Publications (1)

Publication Number Publication Date
ATE545151T1 true ATE545151T1 (de) 2012-02-15

Family

ID=35708624

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06743328T ATE545151T1 (de) 2005-04-22 2006-04-18 Verfahren zum binden zweier aus materialien, die aus halbleitermaterialien ausgewählt wurden, hergestellter wafer

Country Status (9)

Country Link
US (1) US7419884B2 (de)
EP (1) EP1872388B1 (de)
JP (1) JP4976372B2 (de)
KR (1) KR100904873B1 (de)
CN (1) CN101138071B (de)
AT (1) ATE545151T1 (de)
FR (1) FR2884966B1 (de)
TW (1) TWI305010B (de)
WO (1) WO2006111533A1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion
FR2912839B1 (fr) 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
EP1986230A2 (de) * 2007-04-25 2008-10-29 Semiconductor Energy Laboratory Co., Ltd. Verfahren zur Herstellung eines SOI-Substrats und Verfahren zur Herstellung einer Halbleitervorrichtung
US9059247B2 (en) * 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8119490B2 (en) * 2008-02-04 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
KR100958279B1 (ko) * 2008-02-25 2010-05-19 참앤씨(주) 웨이퍼 본딩방법 및 웨이퍼 본딩장치
FR2938702B1 (fr) * 2008-11-19 2011-03-04 Soitec Silicon On Insulator Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
FR2965974B1 (fr) * 2010-10-12 2013-11-29 Soitec Silicon On Insulator Procédé de collage moléculaire de substrats en silicium et en verre
CN105374667B (zh) * 2011-01-25 2019-01-11 Ev 集团 E·索尔纳有限责任公司 用于永久接合晶片的方法
KR102353489B1 (ko) * 2011-01-25 2022-01-19 에베 그룹 에. 탈너 게엠베하 웨이퍼들의 영구적 결합을 위한 방법
CN108470679B (zh) * 2011-01-25 2022-03-29 Ev 集团 E·索尔纳有限责任公司 用于永久接合晶片的方法
WO2012136267A1 (de) * 2011-04-08 2012-10-11 Ev Group E. Thallner Gmbh Verfahren zum permanenten bonden von wafern
US8975158B2 (en) * 2011-04-08 2015-03-10 Ev Group E. Thallner Gmbh Method for permanently bonding wafers
EP2695181B1 (de) * 2011-04-08 2015-06-24 Ev Group E. Thallner GmbH Verfahren zum permanenten bonden von wafern
US9329336B2 (en) 2012-07-06 2016-05-03 Micron Technology, Inc. Method of forming a hermetically sealed fiber to chip connection
CN107195541B (zh) * 2012-07-24 2020-07-24 Ev 集团 E·索尔纳有限责任公司 永久结合晶圆的方法及装置
KR101739210B1 (ko) * 2012-07-26 2017-05-23 에베 그룹 에. 탈너 게엠베하 기판을 본딩하기 위한 방법
EP2894671B1 (de) 2012-09-07 2022-06-08 Kyocera Corporation Verbundsubstrat und herstellungsverfahren dafür
JP6106239B2 (ja) * 2015-09-30 2017-03-29 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウェハを恒久的にボンディングするための方法
JP2016178340A (ja) * 2016-06-15 2016-10-06 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウエハの永久接合方法
JP6679666B2 (ja) * 2018-07-05 2020-04-15 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウエハの永久接合方法
KR20200015264A (ko) * 2018-08-03 2020-02-12 삼성전자주식회사 웨이퍼 접합 방법 및 웨이퍼 접합 시스템
US10978292B2 (en) * 2019-05-29 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Cuprous oxide devices and formation methods
JP7592118B2 (ja) * 2021-11-26 2024-11-29 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウエハの永久接合方法
CN114582781A (zh) * 2022-03-11 2022-06-03 深圳先进电子材料国际创新研究院 一种电磁场辅助激光解键合的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3294934B2 (ja) * 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
EP1018153A1 (de) * 1997-08-29 2000-07-12 Sharon N. Farrens In sito-plasmaverbindungsverfahren für scheiben
JP3582566B2 (ja) * 1997-12-22 2004-10-27 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US6780759B2 (en) * 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
US7078317B2 (en) * 2004-08-06 2006-07-18 Silicon Genesis Corporation Method and system for source switching and in-situ plasma bonding
US7261793B2 (en) 2004-08-13 2007-08-28 Hewlett-Packard Development Company, L.P. System and method for low temperature plasma-enhanced bonding

Also Published As

Publication number Publication date
KR100904873B1 (ko) 2009-06-26
EP1872388B1 (de) 2012-02-08
JP2008535230A (ja) 2008-08-28
KR20070114769A (ko) 2007-12-04
TWI305010B (en) 2009-01-01
EP1872388A1 (de) 2008-01-02
FR2884966A1 (fr) 2006-10-27
US7419884B2 (en) 2008-09-02
CN101138071A (zh) 2008-03-05
CN101138071B (zh) 2012-01-11
WO2006111533A1 (en) 2006-10-26
FR2884966B1 (fr) 2007-08-17
US20060240642A1 (en) 2006-10-26
TW200710971A (en) 2007-03-16
JP4976372B2 (ja) 2012-07-18

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