ATE545934T1 - Speichersystem - Google Patents

Speichersystem

Info

Publication number
ATE545934T1
ATE545934T1 AT08842619T AT08842619T ATE545934T1 AT E545934 T1 ATE545934 T1 AT E545934T1 AT 08842619 T AT08842619 T AT 08842619T AT 08842619 T AT08842619 T AT 08842619T AT E545934 T1 ATE545934 T1 AT E545934T1
Authority
AT
Austria
Prior art keywords
memory
blocks
erasure
bad blocks
sub
Prior art date
Application number
AT08842619T
Other languages
English (en)
Inventor
Daisaburo Takashima
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Application granted granted Critical
Publication of ATE545934T1 publication Critical patent/ATE545934T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/886—Masking faults in memories by using spares or by reconfiguring with partially good memories combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
AT08842619T 2007-10-26 2008-10-03 Speichersystem ATE545934T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007278623A JP2009110053A (ja) 2007-10-26 2007-10-26 メモリシステム
PCT/JP2008/068405 WO2009054272A1 (en) 2007-10-26 2008-10-03 Memory system

Publications (1)

Publication Number Publication Date
ATE545934T1 true ATE545934T1 (de) 2012-03-15

Family

ID=40220716

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08842619T ATE545934T1 (de) 2007-10-26 2008-10-03 Speichersystem

Country Status (7)

Country Link
US (1) US8510498B2 (de)
EP (1) EP2106610B1 (de)
JP (1) JP2009110053A (de)
KR (1) KR101109370B1 (de)
CN (1) CN101622676A (de)
AT (1) ATE545934T1 (de)
WO (1) WO2009054272A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4691123B2 (ja) 2008-03-01 2011-06-01 株式会社東芝 メモリシステム
KR101269366B1 (ko) 2009-02-12 2013-05-29 가부시끼가이샤 도시바 메모리 시스템 및 메모리 시스템의 제어 방법
CN102402485B (zh) * 2010-09-16 2014-05-28 安凯(广州)微电子技术有限公司 Nandflash参数探测方法
KR101751506B1 (ko) 2011-03-28 2017-06-29 삼성전자주식회사 불휘발성 메모리 장치 및 그것의 배드 영역 관리 방법
US8924636B2 (en) 2012-02-23 2014-12-30 Kabushiki Kaisha Toshiba Management information generating method, logical block constructing method, and semiconductor memory device
US9418700B2 (en) * 2012-06-29 2016-08-16 Intel Corporation Bad block management mechanism
CN104021816B (zh) * 2013-03-01 2017-03-29 安凯(广州)微电子技术有限公司 一种测试nftl的方法及系统
KR102231441B1 (ko) * 2014-12-17 2021-03-25 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR20160094154A (ko) * 2015-01-30 2016-08-09 에스케이하이닉스 주식회사 데이터 전송 회로
JP6765321B2 (ja) * 2017-02-28 2020-10-07 キオクシア株式会社 メモリシステムおよび制御方法
KR20190041082A (ko) * 2017-10-12 2019-04-22 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
KR102473662B1 (ko) * 2017-10-18 2022-12-02 삼성전자주식회사 반도체 소자의 제조 방법
JP7077151B2 (ja) * 2018-06-06 2022-05-30 キオクシア株式会社 メモリシステム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09282862A (ja) * 1996-04-11 1997-10-31 Mitsubishi Electric Corp メモリカード
US7143227B2 (en) 2003-02-18 2006-11-28 Dot Hill Systems Corporation Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller
JP2004265162A (ja) * 2003-03-03 2004-09-24 Renesas Technology Corp 記憶装置およびアドレス管理方法
CN100511478C (zh) * 2004-06-30 2009-07-08 深圳市朗科科技股份有限公司 对闪存数据的存取进行管理的方法
CN1979449B (zh) * 2005-12-08 2010-10-27 群联电子股份有限公司 逻辑区块与物理区块形成弹性对应的方法

Also Published As

Publication number Publication date
US20100325343A1 (en) 2010-12-23
CN101622676A (zh) 2010-01-06
EP2106610A1 (de) 2009-10-07
KR101109370B1 (ko) 2012-01-30
US8510498B2 (en) 2013-08-13
WO2009054272A1 (en) 2009-04-30
JP2009110053A (ja) 2009-05-21
KR20090117927A (ko) 2009-11-16
EP2106610B1 (de) 2012-02-15

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