ATE548695T1 - Softwaregesteuerte cache-speicherkonfiguration - Google Patents

Softwaregesteuerte cache-speicherkonfiguration

Info

Publication number
ATE548695T1
ATE548695T1 AT01401532T AT01401532T ATE548695T1 AT E548695 T1 ATE548695 T1 AT E548695T1 AT 01401532 T AT01401532 T AT 01401532T AT 01401532 T AT01401532 T AT 01401532T AT E548695 T1 ATE548695 T1 AT E548695T1
Authority
AT
Austria
Prior art keywords
cache
tag
qualifier
response
data
Prior art date
Application number
AT01401532T
Other languages
English (en)
Inventor
Gerard Chauvel
Inverno Dominique D
Serge Lasserre
Original Assignee
Texas Instruments France
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP00402331A external-priority patent/EP1182559B1/de
Priority claimed from EP00403538A external-priority patent/EP1215583A1/de
Application filed by Texas Instruments France, Texas Instruments Inc filed Critical Texas Instruments France
Application granted granted Critical
Publication of ATE548695T1 publication Critical patent/ATE548695T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/815—Virtual
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT01401532T 2000-08-21 2001-06-13 Softwaregesteuerte cache-speicherkonfiguration ATE548695T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00402331A EP1182559B1 (de) 2000-08-21 2000-08-21 Mikroprozessor
EP00403538A EP1215583A1 (de) 2000-12-15 2000-12-15 Cache-Speicher dessen Tag-Einträge zusätzliche Qualifizierungsfelder enthalten

Publications (1)

Publication Number Publication Date
ATE548695T1 true ATE548695T1 (de) 2012-03-15

Family

ID=26073549

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01401532T ATE548695T1 (de) 2000-08-21 2001-06-13 Softwaregesteuerte cache-speicherkonfiguration

Country Status (2)

Country Link
US (1) US6766421B2 (de)
AT (1) ATE548695T1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231501B2 (en) * 2004-03-30 2007-06-12 Ibm Corporation Method for avoiding aliased tokens during abnormal communications
EP1605360B1 (de) * 2004-06-08 2010-02-17 Freescale Semiconductors, Inc. Aufrechterhaltung der Cachespeicherkoherenz zum direkten Zugriff (DMA), Abschluss einer Aufgabe, zur Synchronisierung
US7865691B2 (en) 2004-08-31 2011-01-04 Freescale Semiconductor, Inc. Virtual address cache and method for sharing data using a unique task identifier
WO2006061767A1 (en) * 2004-12-10 2006-06-15 Koninklijke Philips Electronics N.V. Data processing system and method for cache replacement
US7577870B2 (en) * 2005-12-21 2009-08-18 The Boeing Company Method and system for controlling command execution
GB2449454B (en) * 2007-05-22 2011-08-24 Advanced Risc Mach Ltd Control data modification within a cache memory
US9195625B2 (en) * 2009-10-29 2015-11-24 Freescale Semiconductor, Inc. Interconnect controller for a data processing device with transaction tag locking and method therefor
US8504777B2 (en) * 2010-09-21 2013-08-06 Freescale Semiconductor, Inc. Data processor for processing decorated instructions with cache bypass
WO2014142867A1 (en) 2013-03-14 2014-09-18 Intel Corporation Power efficient level one data cache access with pre-validated tags
GB2566470B (en) * 2017-09-13 2021-02-10 Advanced Risc Mach Ltd Cache storage
KR102570030B1 (ko) * 2023-04-19 2023-08-28 메티스엑스 주식회사 멀티프로세서 시스템 및 이의 데이터 관리 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2210480B (en) 1987-10-02 1992-01-29 Sun Microsystems Inc Flush support
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5675763A (en) * 1992-07-15 1997-10-07 Digital Equipment Corporation Cache memory system and method for selectively removing stale aliased entries
US5778434A (en) * 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
US5809522A (en) * 1995-12-18 1998-09-15 Advanced Micro Devices, Inc. Microprocessor system with process identification tag entries to reduce cache flushing after a context switch
US5778431A (en) * 1995-12-19 1998-07-07 Advanced Micro Devices, Inc. System and apparatus for partially flushing cache memory
US5974438A (en) 1996-12-31 1999-10-26 Compaq Computer Corporation Scoreboard for cached multi-thread processes
JPH10340197A (ja) 1997-06-09 1998-12-22 Nec Corp キャッシング制御方法及びマイクロコンピュータ
US6119167A (en) * 1997-07-11 2000-09-12 Phone.Com, Inc. Pushing and pulling data in networks
US6349363B2 (en) 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section

Also Published As

Publication number Publication date
US6766421B2 (en) 2004-07-20
US20020065980A1 (en) 2002-05-30

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