ATE549797T1 - Verstärkte passgatestrukturen zur leckstromverringerung - Google Patents

Verstärkte passgatestrukturen zur leckstromverringerung

Info

Publication number
ATE549797T1
ATE549797T1 AT05778119T AT05778119T ATE549797T1 AT E549797 T1 ATE549797 T1 AT E549797T1 AT 05778119 T AT05778119 T AT 05778119T AT 05778119 T AT05778119 T AT 05778119T AT E549797 T1 ATE549797 T1 AT E549797T1
Authority
AT
Austria
Prior art keywords
passgate
structures
leakage current
sub
voltage
Prior art date
Application number
AT05778119T
Other languages
English (en)
Inventor
Henry Y Lui
Malik Kabani
Rakesh Patel
Tim Tri Hoang
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of ATE549797T1 publication Critical patent/ATE549797T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
AT05778119T 2004-08-03 2005-08-02 Verstärkte passgatestrukturen zur leckstromverringerung ATE549797T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/910,891 US7292065B2 (en) 2004-08-03 2004-08-03 Enhanced passgate structures for reducing leakage current
PCT/US2005/027416 WO2006017501A1 (en) 2004-08-03 2005-08-02 Enhanced passgate structures for reducing leakage current

Publications (1)

Publication Number Publication Date
ATE549797T1 true ATE549797T1 (de) 2012-03-15

Family

ID=35756807

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05778119T ATE549797T1 (de) 2004-08-03 2005-08-02 Verstärkte passgatestrukturen zur leckstromverringerung

Country Status (6)

Country Link
US (1) US7292065B2 (de)
EP (1) EP1779513B1 (de)
JP (1) JP2008509604A (de)
CN (1) CN101027838B (de)
AT (1) ATE549797T1 (de)
WO (1) WO2006017501A1 (de)

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US7673202B2 (en) * 2006-09-28 2010-03-02 Cisco Technology, Inc. Single event upset test circuit and methodology
US7893723B2 (en) * 2007-12-29 2011-02-22 Texas Instruments Incorporated Minimizing leakage in logic designs
JP5414061B2 (ja) * 2010-03-24 2014-02-12 独立行政法人産業技術総合研究所 パストランジスタを用いた論理回路、セレクター回路及び集積回路
US8581625B2 (en) 2011-05-19 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
US8804407B1 (en) 2011-07-12 2014-08-12 Altera Corporation PMOS pass gate
US8723592B2 (en) * 2011-08-12 2014-05-13 Nxp B.V. Adjustable body bias circuit
US8705605B1 (en) 2011-11-03 2014-04-22 Altera Corporation Technique for providing loopback testing with single stage equalizer
US8995175B1 (en) * 2012-01-13 2015-03-31 Altera Corporation Memory circuit with PMOS access transistors
US9628081B2 (en) * 2014-08-12 2017-04-18 Xilinx, Inc. Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit
CN112951830B (zh) * 2021-02-01 2023-02-07 泉芯集成电路制造(济南)有限公司 集成电路器件、存储器和电子设备

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US4831596A (en) * 1987-05-01 1989-05-16 Texas Instruments Incorporated Pass gate with low transistor junction breakdown susceptibility
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US6563367B1 (en) * 2000-08-16 2003-05-13 Altera Corporation Interconnection switch structures
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CN1399407A (zh) * 2001-07-26 2003-02-26 中国科学院微电子中心 自举式－互补传输门电荷恢复低功耗电路结构
US6621325B2 (en) * 2001-09-18 2003-09-16 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
CN100489797C (zh) * 2001-10-11 2009-05-20 阿尔特拉公司 可编程逻辑设备上的错误检测
JP3522248B2 (ja) * 2001-10-15 2004-04-26 ローム株式会社 半導体集積回路装置
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Also Published As

Publication number Publication date
JP2008509604A (ja) 2008-03-27
CN101027838B (zh) 2010-10-27
US7292065B2 (en) 2007-11-06
EP1779513A1 (de) 2007-05-02
CN101027838A (zh) 2007-08-29
EP1779513B1 (de) 2012-03-14
WO2006017501A1 (en) 2006-02-16
US20060028240A1 (en) 2006-02-09

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