ATE552611T1 - Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte - Google Patents
Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichteInfo
- Publication number
- ATE552611T1 ATE552611T1 AT04703076T AT04703076T ATE552611T1 AT E552611 T1 ATE552611 T1 AT E552611T1 AT 04703076 T AT04703076 T AT 04703076T AT 04703076 T AT04703076 T AT 04703076T AT E552611 T1 ATE552611 T1 AT E552611T1
- Authority
- AT
- Austria
- Prior art keywords
- defect density
- sige
- sgoi
- stacking fault
- high relaxation
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
- H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
- H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3204—Materials thereof being Group IVA semiconducting materials
- H10P14/3211—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6322—Formation by thermal treatments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
Landscapes
- Recrystallisation Techniques (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2004/001555 WO2005078786A1 (en) | 2004-01-16 | 2004-01-16 | Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE552611T1 true ATE552611T1 (de) | 2012-04-15 |
Family
ID=34862309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04703076T ATE552611T1 (de) | 2004-01-16 | 2004-01-16 | Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7550370B2 (de) |
| EP (1) | EP1709671B1 (de) |
| JP (1) | JP4686480B2 (de) |
| KR (1) | KR100925310B1 (de) |
| CN (1) | CN100459072C (de) |
| AT (1) | ATE552611T1 (de) |
| WO (1) | WO2005078786A1 (de) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
| ATE552611T1 (de) * | 2004-01-16 | 2012-04-15 | Ibm | Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte |
| JP2006080278A (ja) * | 2004-09-09 | 2006-03-23 | Toshiba Ceramics Co Ltd | 歪みシリコンウエハおよびその製造方法 |
| EP1763069B1 (de) | 2005-09-07 | 2016-04-13 | Soitec | Herstellungsverfahren einer Heterostruktur |
| FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
| US20070154637A1 (en) * | 2005-12-19 | 2007-07-05 | Rohm And Haas Electronic Materials Llc | Organometallic composition |
| DE102006020825A1 (de) * | 2006-05-04 | 2007-11-08 | Siltronic Ag | Verfahren zur Herstellung einer Schichtenstruktur |
| JP5018066B2 (ja) * | 2006-12-19 | 2012-09-05 | 信越半導体株式会社 | 歪Si基板の製造方法 |
| WO2010013325A1 (ja) * | 2008-07-30 | 2010-02-04 | 株式会社ニレコ | 分光測光装置 |
| CN101388331B (zh) * | 2008-10-31 | 2010-08-25 | 上海新傲科技股份有限公司 | 制备绝缘体上硅材料的内热氧化方法 |
| DE102009010883B4 (de) * | 2009-02-27 | 2011-05-26 | Amd Fab 36 Limited Liability Company & Co. Kg | Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses |
| FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
| US20110086444A1 (en) * | 2009-10-14 | 2011-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for producing substrates free of patterns using an alpha stepper to ensure results |
| US8703551B2 (en) * | 2011-05-06 | 2014-04-22 | Globalfoundries Inc. | Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter |
| JP2013055231A (ja) * | 2011-09-05 | 2013-03-21 | Shin Etsu Handotai Co Ltd | エピタキシャルウェーハの製造方法 |
| CN102290369B (zh) * | 2011-09-22 | 2013-12-04 | 中国科学院上海微系统与信息技术研究所 | 一种薄goi晶片及其制备方法 |
| US8883598B2 (en) * | 2012-03-05 | 2014-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thin capped channel layers of semiconductor devices and methods of forming the same |
| CN104078407B (zh) * | 2013-03-29 | 2018-12-04 | 济南晶正电子科技有限公司 | 薄膜和制造薄膜的方法 |
| US9324843B2 (en) | 2014-09-05 | 2016-04-26 | International Business Machines Corporation | High germanium content silicon germanium fins |
| KR102259328B1 (ko) | 2014-10-10 | 2021-06-02 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US9608067B2 (en) * | 2015-03-30 | 2017-03-28 | International Business Machines Corporation | Hybrid aspect ratio trapping |
| KR102326316B1 (ko) | 2015-04-10 | 2021-11-16 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| CN106257631A (zh) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法、电子装置 |
| US9818761B2 (en) | 2015-06-25 | 2017-11-14 | International Business Machines Corporation | Selective oxidation for making relaxed silicon germanium on insulator structures |
| US9362311B1 (en) | 2015-07-24 | 2016-06-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US9530669B1 (en) * | 2015-11-30 | 2016-12-27 | International Business Machines Corporation | Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity |
| US9570298B1 (en) | 2015-12-09 | 2017-02-14 | International Business Machines Corporation | Localized elastic strain relaxed buffer |
| FR3061803B1 (fr) * | 2017-01-11 | 2019-08-16 | Soitec | Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat |
| FR3061988B1 (fr) * | 2017-01-13 | 2019-11-01 | Soitec | Procede de lissage de surface d'un substrat semiconducteur sur isolant |
| CN111551762A (zh) * | 2020-05-14 | 2020-08-18 | 中国电子科技集团公司第二十四研究所 | 一种基于原位腐蚀的锗外延层缺陷密度检测方法 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4409260A (en) * | 1979-08-15 | 1983-10-11 | Hughes Aircraft Company | Process for low-temperature surface layer oxidation of a semiconductor substrate |
| US5298457A (en) * | 1993-07-01 | 1994-03-29 | G. I. Corporation | Method of making semiconductor devices using epitaxial techniques to form Si/Si-Ge interfaces and inverting the material |
| JP3361922B2 (ja) * | 1994-09-13 | 2003-01-07 | 株式会社東芝 | 半導体装置 |
| US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
| US6066576A (en) * | 1997-06-04 | 2000-05-23 | Micron Technology, Inc. | Method for forming oxide using high pressure |
| FR2773177B1 (fr) * | 1997-12-29 | 2000-03-17 | France Telecom | Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus |
| JP3884203B2 (ja) * | 1998-12-24 | 2007-02-21 | 株式会社東芝 | 半導体装置の製造方法 |
| US6346453B1 (en) * | 2000-01-27 | 2002-02-12 | Sige Microsystems Inc. | Method of producing a SI-GE base heterojunction bipolar device |
| JP2001351869A (ja) * | 2000-06-09 | 2001-12-21 | Mitsubishi Materials Silicon Corp | シリコンウェーハおよびその製造方法 |
| US6524935B1 (en) | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
| US6890835B1 (en) * | 2000-10-19 | 2005-05-10 | International Business Machines Corporation | Layer transfer of low defect SiGe using an etch-back process |
| TWI313059B (de) * | 2000-12-08 | 2009-08-01 | Sony Corporatio | |
| US6448152B1 (en) * | 2001-02-20 | 2002-09-10 | Silicon Genesis Corporation | Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer |
| US6646322B2 (en) | 2001-03-02 | 2003-11-11 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| JP2002289533A (ja) * | 2001-03-26 | 2002-10-04 | Kentaro Sawano | 半導体表面の研磨方法、半導体デバイスの製造方法および半導体デバイス |
| US6660607B2 (en) * | 2001-03-30 | 2003-12-09 | International Business Machines Corporation | Method for fabricating heterojunction bipolar transistors |
| US20020168802A1 (en) * | 2001-05-14 | 2002-11-14 | Hsu Sheng Teng | SiGe/SOI CMOS and method of making the same |
| US6855436B2 (en) * | 2003-05-30 | 2005-02-15 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
| US6593625B2 (en) | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
| JP4378904B2 (ja) * | 2001-09-28 | 2009-12-09 | 株式会社Sumco | 半導体基板の製造方法及び電界効果型トランジスタの製造方法 |
| JP2003158250A (ja) * | 2001-10-30 | 2003-05-30 | Sharp Corp | SiGe/SOIのCMOSおよびその製造方法 |
| US6805962B2 (en) | 2002-01-23 | 2004-10-19 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
| US7026249B2 (en) * | 2003-05-30 | 2006-04-11 | International Business Machines Corporation | SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth |
| JP2004363199A (ja) * | 2003-06-02 | 2004-12-24 | Sumitomo Mitsubishi Silicon Corp | 半導体基板の製造方法 |
| JP4037803B2 (ja) * | 2003-07-24 | 2008-01-23 | 株式会社東芝 | Sgoi基板の製造方法 |
| ATE552611T1 (de) * | 2004-01-16 | 2012-04-15 | Ibm | Verfahren zur erzeugung von dünnen sgoi-wafern mit hoher relaxations- und niedriger stapelfehlerdefektdichte |
| US7235812B2 (en) * | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
-
2004
- 2004-01-16 AT AT04703076T patent/ATE552611T1/de active
- 2004-01-16 WO PCT/US2004/001555 patent/WO2005078786A1/en not_active Ceased
- 2004-01-16 US US10/597,066 patent/US7550370B2/en not_active Expired - Fee Related
- 2004-01-16 EP EP04703076A patent/EP1709671B1/de not_active Expired - Lifetime
- 2004-01-16 KR KR1020067013849A patent/KR100925310B1/ko not_active Expired - Fee Related
- 2004-01-16 JP JP2006549218A patent/JP4686480B2/ja not_active Expired - Fee Related
- 2004-01-16 CN CNB2004800405182A patent/CN100459072C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR100925310B1 (ko) | 2009-11-04 |
| CN1906742A (zh) | 2007-01-31 |
| KR20060123471A (ko) | 2006-12-01 |
| CN100459072C (zh) | 2009-02-04 |
| EP1709671A4 (de) | 2010-06-16 |
| EP1709671B1 (de) | 2012-04-04 |
| US20070128840A1 (en) | 2007-06-07 |
| JP2007518264A (ja) | 2007-07-05 |
| WO2005078786A1 (en) | 2005-08-25 |
| US7550370B2 (en) | 2009-06-23 |
| EP1709671A1 (de) | 2006-10-11 |
| JP4686480B2 (ja) | 2011-05-25 |
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