ATE555478T1 - Verfahren und vorrichtung zur maximierung der bandbreite eines dram speichers - Google Patents
Verfahren und vorrichtung zur maximierung der bandbreite eines dram speichersInfo
- Publication number
- ATE555478T1 ATE555478T1 AT03714158T AT03714158T ATE555478T1 AT E555478 T1 ATE555478 T1 AT E555478T1 AT 03714158 T AT03714158 T AT 03714158T AT 03714158 T AT03714158 T AT 03714158T AT E555478 T1 ATE555478 T1 AT E555478T1
- Authority
- AT
- Austria
- Prior art keywords
- data unit
- buffer
- buffers
- index
- maximizing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Transfer Systems (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/103,956 US6769047B2 (en) | 2002-03-21 | 2002-03-21 | Method and system for maximizing DRAM memory bandwidth through storing memory bank indexes in associated buffers |
| PCT/US2003/007914 WO2003081598A2 (en) | 2002-03-21 | 2003-03-13 | Method and system for maximizing dram memory bandwidth |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE555478T1 true ATE555478T1 (de) | 2012-05-15 |
Family
ID=28040479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT03714158T ATE555478T1 (de) | 2002-03-21 | 2003-03-13 | Verfahren und vorrichtung zur maximierung der bandbreite eines dram speichers |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6769047B2 (de) |
| EP (1) | EP1485919B1 (de) |
| CN (1) | CN100487815C (de) |
| AT (1) | ATE555478T1 (de) |
| AU (1) | AU2003218167A1 (de) |
| TW (1) | TWI301986B (de) |
| WO (1) | WO2003081598A2 (de) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060064535A1 (en) * | 2004-09-22 | 2006-03-23 | Walker Robert M | Efficient multi-bank memory queuing system |
| US7523264B1 (en) | 2005-12-15 | 2009-04-21 | Nvidia Corporation | Apparatus, system, and method for dependent computations of streaming multiprocessors |
| US7698498B2 (en) * | 2005-12-29 | 2010-04-13 | Intel Corporation | Memory controller with bank sorting and scheduling |
| US7492368B1 (en) * | 2006-01-24 | 2009-02-17 | Nvidia Corporation | Apparatus, system, and method for coalescing parallel memory requests |
| US8081184B1 (en) * | 2006-05-05 | 2011-12-20 | Nvidia Corporation | Pixel shader program thread assembly |
| US20090019238A1 (en) * | 2007-07-10 | 2009-01-15 | Brian David Allison | Memory Controller Read Queue Dynamic Optimization of Command Selection |
| US7761669B2 (en) * | 2007-07-10 | 2010-07-20 | International Business Machines Corporation | Memory controller granular read queue dynamic optimization of command selection |
| US8914612B2 (en) * | 2007-10-29 | 2014-12-16 | Conversant Intellectual Property Management Inc. | Data processing with time-based memory access |
| US8627009B2 (en) * | 2008-09-16 | 2014-01-07 | Mosaid Technologies Incorporated | Cache filtering method and apparatus |
| US20120066444A1 (en) * | 2010-09-14 | 2012-03-15 | Advanced Micro Devices, Inc. | Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation |
| US10380024B2 (en) * | 2017-12-05 | 2019-08-13 | Nanya Technology Corporation | DRAM and method of operating the same in an hierarchical memory system |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5630096A (en) * | 1995-05-10 | 1997-05-13 | Microunity Systems Engineering, Inc. | Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order |
| US5598374A (en) * | 1995-07-14 | 1997-01-28 | Cirrus Logic, Inc. | Pipeland address memories, and systems and methods using the same |
| US6510474B1 (en) * | 1998-11-16 | 2003-01-21 | Infineon Technologies Ag | Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests |
| US6216178B1 (en) * | 1998-11-16 | 2001-04-10 | Infineon Technologies Ag | Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution |
| US6539440B1 (en) * | 1998-11-16 | 2003-03-25 | Infineon Ag | Methods and apparatus for prediction of the time between two consecutive memory accesses |
| US6571307B1 (en) * | 1999-10-19 | 2003-05-27 | Advanced Micro Devices, Inc. | Multiple purpose bus for a simultaneous operation flash memory device |
| US6310880B1 (en) | 2000-03-17 | 2001-10-30 | Silicon Aquarius, Inc. | Content addressable memory cells and systems and devices using the same |
| JP4121690B2 (ja) * | 2000-05-29 | 2008-07-23 | 富士通株式会社 | 半導体記憶装置 |
| US6546453B1 (en) * | 2000-08-31 | 2003-04-08 | Compaq Information Technologies Group, L.P. | Proprammable DRAM address mapping mechanism |
| US6587920B2 (en) * | 2000-11-30 | 2003-07-01 | Mosaid Technologies Incorporated | Method and apparatus for reducing latency in a memory system |
-
2002
- 2002-03-21 US US10/103,956 patent/US6769047B2/en not_active Expired - Fee Related
-
2003
- 2003-03-13 CN CNB038108119A patent/CN100487815C/zh not_active Expired - Fee Related
- 2003-03-13 AU AU2003218167A patent/AU2003218167A1/en not_active Abandoned
- 2003-03-13 AT AT03714158T patent/ATE555478T1/de active
- 2003-03-13 EP EP03714158A patent/EP1485919B1/de not_active Expired - Lifetime
- 2003-03-13 WO PCT/US2003/007914 patent/WO2003081598A2/en not_active Ceased
- 2003-03-18 TW TW092105905A patent/TWI301986B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US20030182490A1 (en) | 2003-09-25 |
| EP1485919B1 (de) | 2012-04-25 |
| CN100487815C (zh) | 2009-05-13 |
| WO2003081598A3 (en) | 2003-11-13 |
| US6769047B2 (en) | 2004-07-27 |
| CN1723506A (zh) | 2006-01-18 |
| AU2003218167A8 (en) | 2003-10-08 |
| TW200400515A (en) | 2004-01-01 |
| EP1485919A2 (de) | 2004-12-15 |
| WO2003081598A2 (en) | 2003-10-02 |
| AU2003218167A1 (en) | 2003-10-08 |
| TWI301986B (en) | 2008-10-11 |
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