ATE557289T1 - Integriertes testverfahren einer leitung - Google Patents

Integriertes testverfahren einer leitung

Info

Publication number
ATE557289T1
ATE557289T1 AT10156773T AT10156773T ATE557289T1 AT E557289 T1 ATE557289 T1 AT E557289T1 AT 10156773 T AT10156773 T AT 10156773T AT 10156773 T AT10156773 T AT 10156773T AT E557289 T1 ATE557289 T1 AT E557289T1
Authority
AT
Austria
Prior art keywords
line
logical level
pin
measurement
instant
Prior art date
Application number
AT10156773T
Other languages
English (en)
Inventor
Stephane Bouyat
Original Assignee
Thales Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Sa filed Critical Thales Sa
Application granted granted Critical
Publication of ATE557289T1 publication Critical patent/ATE557289T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT10156773T 2009-03-17 2010-03-17 Integriertes testverfahren einer leitung ATE557289T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0901234A FR2943435B1 (fr) 2009-03-17 2009-03-17 Procedes de test integre d'une ligne.

Publications (1)

Publication Number Publication Date
ATE557289T1 true ATE557289T1 (de) 2012-05-15

Family

ID=41397501

Family Applications (1)

Application Number Title Priority Date Filing Date
AT10156773T ATE557289T1 (de) 2009-03-17 2010-03-17 Integriertes testverfahren einer leitung

Country Status (6)

Country Link
US (1) US8339154B2 (de)
EP (1) EP2230528B1 (de)
CN (1) CN101943735A (de)
AT (1) ATE557289T1 (de)
FR (1) FR2943435B1 (de)
RU (1) RU2010109853A (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102901905B (zh) * 2012-11-12 2015-06-10 株洲南车时代电气股份有限公司 一种并行总线测试方法
EP2887079A1 (de) * 2013-12-20 2015-06-24 Electrolux Appliances Aktiebolag Elektronisches System und Verfahren zur Prüfung kapazitiver Leiterbahnen
DE102017208171B3 (de) * 2017-05-15 2018-10-11 Pepperl + Fuchs Gmbh Verfahren zur Überwachung eines Betriebs einer binären Schnittstelle und entsprechende binäre Schnittstelle
DE102017208170A1 (de) * 2017-05-15 2018-11-15 Pepperl + Fuchs Gmbh Verfahren zur Überwachung eines Betriebs einer binären Schnittstelle und entsprechende binäre Schnittstelle
CN109633362A (zh) * 2019-01-30 2019-04-16 努比亚技术有限公司 智能终端设计电路、智能终端及智能终端短路检测方法
TWI864717B (zh) * 2023-04-28 2024-12-01 南亞科技股份有限公司 記憶體測試系統及記憶體測試方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100440366B1 (ko) * 1995-10-20 2004-11-16 코닌클리케 필립스 일렉트로닉스 엔.브이. 테스트가능회로및테스트방법
JP4080550B2 (ja) * 1998-02-05 2008-04-23 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 接続テスト方法
US6266793B1 (en) * 1999-02-26 2001-07-24 Intel Corporation JTAG boundary scan cell with enhanced testability feature
US6507215B1 (en) * 2001-04-18 2003-01-14 Cygnal Integrated Products, Inc. Programmable driver for an I/O pin of an integrated circuit
US6918074B2 (en) * 2002-06-28 2005-07-12 Intel Corporation At speed testing asynchronous signals
US20040123195A1 (en) * 2002-12-20 2004-06-24 Rohrbaugh John G. Systems and methods for testing tri-state bus drivers
US7474559B1 (en) * 2005-08-30 2009-01-06 Xilinx, Inc. Circuit and method for employing unused configuration memory cells as scratchpad memory
US7406642B1 (en) * 2005-10-03 2008-07-29 Altera Corporation Techniques for capturing signals at output pins in a programmable logic integrated circuit
US7973563B2 (en) * 2008-02-15 2011-07-05 Silicon Labs Spectra, Inc. Programmable IO architecture

Also Published As

Publication number Publication date
FR2943435A1 (fr) 2010-09-24
US8339154B2 (en) 2012-12-25
RU2010109853A (ru) 2011-09-27
CN101943735A (zh) 2011-01-12
FR2943435B1 (fr) 2012-01-27
EP2230528B1 (de) 2012-05-09
US20110084723A1 (en) 2011-04-14
EP2230528A1 (de) 2010-09-22

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