ATE57794T1 - Verfahren zur herstellung einer mosspeicheranordnung, welche elektrisch programmierbare und elektrisch loeschbare speicherelemente enthaelt. - Google Patents

Verfahren zur herstellung einer mosspeicheranordnung, welche elektrisch programmierbare und elektrisch loeschbare speicherelemente enthaelt.

Info

Publication number
ATE57794T1
ATE57794T1 AT83300451T AT83300451T ATE57794T1 AT E57794 T1 ATE57794 T1 AT E57794T1 AT 83300451 T AT83300451 T AT 83300451T AT 83300451 T AT83300451 T AT 83300451T AT E57794 T1 ATE57794 T1 AT E57794T1
Authority
AT
Austria
Prior art keywords
substrate
control gates
polysilicon areas
regions
memory cell
Prior art date
Application number
AT83300451T
Other languages
English (en)
Inventor
Te-Long Chiu
Original Assignee
Seeq Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seeq Technology Inc filed Critical Seeq Technology Inc
Application granted granted Critical
Publication of ATE57794T1 publication Critical patent/ATE57794T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AT83300451T 1982-01-29 1983-01-28 Verfahren zur herstellung einer mosspeicheranordnung, welche elektrisch programmierbare und elektrisch loeschbare speicherelemente enthaelt. ATE57794T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/343,845 US4490900A (en) 1982-01-29 1982-01-29 Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein
EP83300451A EP0085551B1 (de) 1982-01-29 1983-01-28 Verfahren zur Herstellung einer MOS-Speicheranordnung, welche elektrisch programmierbare und elektrisch löschbare Speicherelemente enthält

Publications (1)

Publication Number Publication Date
ATE57794T1 true ATE57794T1 (de) 1990-11-15

Family

ID=23347927

Family Applications (1)

Application Number Title Priority Date Filing Date
AT83300451T ATE57794T1 (de) 1982-01-29 1983-01-28 Verfahren zur herstellung einer mosspeicheranordnung, welche elektrisch programmierbare und elektrisch loeschbare speicherelemente enthaelt.

Country Status (4)

Country Link
US (1) US4490900A (de)
EP (1) EP0085551B1 (de)
AT (1) ATE57794T1 (de)
DE (1) DE3381949D1 (de)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric
US4949154A (en) * 1983-02-23 1990-08-14 Texas Instruments, Incorporated Thin dielectrics over polysilicon
US4577390A (en) * 1983-02-23 1986-03-25 Texas Instruments Incorporated Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer
US4876582A (en) * 1983-05-02 1989-10-24 Ncr Corporation Crystallized silicon-on-insulator nonvolatile memory device
DE3483765D1 (de) * 1983-09-28 1991-01-31 Toshiba Kawasaki Kk Elektrisch loeschbare und programmierbare nichtfluechtige halbleiterspeicheranordnung mit zwei gate-elektroden.
US4769340A (en) * 1983-11-28 1988-09-06 Exel Microelectronics, Inc. Method for making electrically programmable memory device by doping the floating gate by implant
EP0164605B1 (de) * 1984-05-17 1990-02-28 Kabushiki Kaisha Toshiba Verfahren zur Herstellung eines nichtflüchtigen Halbleiter-EEPROM-Elementes
EP0215064A1 (de) * 1985-03-08 1987-03-25 Ncr Corporation Nicht-flüchtige feldeffektspeichervorrichtung mit schwebendem gate
US4962322A (en) * 1988-12-05 1990-10-09 Texas Instruments Incorporated Nonvolatible capacitor random access memory
US4939558A (en) * 1985-09-27 1990-07-03 Texas Instruments Incorporated EEPROM memory cell and driving circuitry
US4742492A (en) * 1985-09-27 1988-05-03 Texas Instruments Incorporated EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
US5296396A (en) * 1988-12-05 1994-03-22 Sgs-Thomson Microelectronics S.R.L. Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
US5196914A (en) * 1989-03-15 1993-03-23 Sgs-Thomson Microelectronics S.R.L. Table cloth matrix of EPROM memory cells with an asymmetrical fin
US5017979A (en) 1989-04-28 1991-05-21 Nippondenso Co., Ltd. EEPROM semiconductor memory device
US6373093B2 (en) * 1989-04-28 2002-04-16 Nippondenso Corporation Semiconductor memory device and method of manufacturing the same
US5036378A (en) * 1989-11-01 1991-07-30 At&T Bell Laboratories Memory device
JP2755781B2 (ja) * 1990-04-23 1998-05-25 株式会社東芝 半導体記憶装置およびその製造方法
US5268320A (en) * 1990-12-26 1993-12-07 Intel Corporation Method of increasing the accuracy of an analog circuit employing floating gate memory devices
EP0617461B1 (de) * 1993-03-24 1997-09-10 AT&T Corp. Verfahren zur Bildung dielektrischer Oxynitridschichten bei der Herstellung integrierter Schaltungen
EP0752717A1 (de) * 1995-05-10 1997-01-08 STMicroelectronics S.r.l. Herstellungsverfahren für eine integrierte Schaltung mit Komponenten mit unterschiedlichem Dielektrum
EP0782196A1 (de) * 1995-12-28 1997-07-02 STMicroelectronics S.r.l. Herstellungsverfahren für EEPROM-Speicherbauelemente und dadurch hergestellte EEPROM-Speicherbauelemente
US6749687B1 (en) * 1998-01-09 2004-06-15 Asm America, Inc. In situ growth of oxide and silicon layers
US6518618B1 (en) 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
US6444555B2 (en) * 1999-12-07 2002-09-03 Advanced Micro Devices, Inc. Method for establishing ultra-thin gate insulator using anneal in ammonia
US6709928B1 (en) * 2001-07-31 2004-03-23 Cypress Semiconductor Corporation Semiconductor device having silicon-rich layer and method of manufacturing such a device
US6798693B2 (en) 2001-09-18 2004-09-28 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
WO2003025944A1 (en) 2001-09-18 2003-03-27 Kilopass Technologies, Inc. Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric
US6766960B2 (en) 2001-10-17 2004-07-27 Kilopass Technologies, Inc. Smart card having memory using a breakdown phenomena in an ultra-thin dielectric
US6700151B2 (en) * 2001-10-17 2004-03-02 Kilopass Technologies, Inc. Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric
US6940751B2 (en) * 2002-04-26 2005-09-06 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown
US6992925B2 (en) * 2002-04-26 2006-01-31 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline
US6898116B2 (en) * 2002-04-26 2005-05-24 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection
US6777757B2 (en) * 2002-04-26 2004-08-17 Kilopass Technologies, Inc. High density semiconductor memory cell and memory array using a single transistor
US6650143B1 (en) 2002-07-08 2003-11-18 Kilopass Technologies, Inc. Field programmable gate array based upon transistor gate oxide breakdown
US7042772B2 (en) * 2002-09-26 2006-05-09 Kilopass Technology, Inc. Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US7031209B2 (en) * 2002-09-26 2006-04-18 Kilopass Technology, Inc. Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
US6791891B1 (en) 2003-04-02 2004-09-14 Kilopass Technologies, Inc. Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
US6924664B2 (en) * 2003-08-15 2005-08-02 Kilopass Technologies, Inc. Field programmable gate array
US20050118802A1 (en) * 2003-12-02 2005-06-02 Chang-Sheng Tsao Method for implementing poly pre-doping in deep sub-micron process
US6972986B2 (en) * 2004-02-03 2005-12-06 Kilopass Technologies, Inc. Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown
US7064973B2 (en) * 2004-02-03 2006-06-20 Klp International, Ltd. Combination field programmable gate array allowing dynamic reprogrammability
US20050218929A1 (en) * 2004-04-02 2005-10-06 Man Wang Field programmable gate array logic cell and its derivatives
US8735297B2 (en) 2004-05-06 2014-05-27 Sidense Corporation Reverse optical proximity correction method
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
WO2005109516A1 (en) * 2004-05-06 2005-11-17 Sidense Corp. Split-channel antifuse array architecture
US7755162B2 (en) 2004-05-06 2010-07-13 Sidense Corp. Anti-fuse memory cell
US20050275427A1 (en) * 2004-06-10 2005-12-15 Man Wang Field programmable gate array logic unit and its cluster
US7164290B2 (en) * 2004-06-10 2007-01-16 Klp International, Ltd. Field programmable gate array logic unit and its cluster
US7135886B2 (en) * 2004-09-20 2006-11-14 Klp International, Ltd. Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control
US7193436B2 (en) * 2005-04-18 2007-03-20 Klp International Ltd. Fast processing path using field programmable gate array logic units
JP4649265B2 (ja) * 2005-04-28 2011-03-09 株式会社東芝 不揮発性半導体記憶装置の製造方法
US9449831B2 (en) 2007-05-25 2016-09-20 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8067284B1 (en) 2007-05-25 2011-11-29 Cypress Semiconductor Corporation Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US8283261B2 (en) 2007-05-25 2012-10-09 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US8643124B2 (en) 2007-05-25 2014-02-04 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US20090179253A1 (en) 2007-05-25 2009-07-16 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US7898852B1 (en) 2007-12-27 2011-03-01 Cypress Semiconductor Corporation Trapped-charge non-volatile memory with uniform multilevel programming
US8088683B2 (en) * 2008-03-31 2012-01-03 Cypress Semiconductor Corporation Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
US8685813B2 (en) 2012-02-15 2014-04-01 Cypress Semiconductor Corporation Method of integrating a charge-trapping gate stack into a CMOS flow
CN112908838A (zh) * 2019-11-19 2021-06-04 长鑫存储技术有限公司 改善热处理腔室污染的方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3868187A (en) * 1972-08-31 1975-02-25 Tokyo Shibaura Electric Co Avalanche injection type mos memory
US3919711A (en) * 1973-02-26 1975-11-11 Intel Corp Erasable floating gate device
US3924024A (en) * 1973-04-02 1975-12-02 Ncr Co Process for fabricating MNOS non-volatile memories
JPS571149B2 (de) * 1974-08-28 1982-01-09
US4016588A (en) * 1974-12-27 1977-04-05 Nippon Electric Company, Ltd. Non-volatile semiconductor memory device
NL7500550A (nl) * 1975-01-17 1976-07-20 Philips Nv Halfgeleider-geheugeninrichting.
JPS587923B2 (ja) * 1975-09-06 1983-02-14 イシカワ ジロウ ハグルマケンサホウホウトソウチ
GB1540450A (en) * 1975-10-29 1979-02-14 Intel Corp Self-aligning double polycrystalline silicon etching process
US4115914A (en) * 1976-03-26 1978-09-26 Hughes Aircraft Company Electrically erasable non-volatile semiconductor memory
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
JPS5559729A (en) * 1978-10-27 1980-05-06 Fujitsu Ltd Forming method of semiconductor surface insulating film
JPS5642375A (en) * 1979-08-31 1981-04-20 Fujitsu Ltd Semiconductor nonvolatile memory
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof

Also Published As

Publication number Publication date
EP0085551A3 (en) 1986-06-04
EP0085551B1 (de) 1990-10-24
US4490900A (en) 1985-01-01
EP0085551A2 (de) 1983-08-10
DE3381949D1 (de) 1990-11-29

Similar Documents

Publication Publication Date Title
ATE57794T1 (de) Verfahren zur herstellung einer mosspeicheranordnung, welche elektrisch programmierbare und elektrisch loeschbare speicherelemente enthaelt.
US5231299A (en) Structure and fabrication method for EEPROM memory cell with selective channel implants
US5019879A (en) Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
US4267632A (en) Process for fabricating a high density electrically programmable memory array
US5445981A (en) Method of making shallow trench source EPROM cell
US4376947A (en) Electrically programmable floating gate semiconductor memory device
US5021848A (en) Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5476801A (en) Spacer flash cell process
US5173436A (en) Method of manufacturing an EEPROM with trench-isolated bitlines
US5094968A (en) Fabricating a narrow width EEPROM with single diffusion electrode formation
US5102814A (en) Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions
US4112509A (en) Electrically alterable floating gate semiconductor memory device
US4467453A (en) Electrically programmable floating gate semiconductor memory device
DE69312676D1 (de) Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz
US4514897A (en) Electrically programmable floating gate semiconductor memory device
KR940001426A (ko) 폴리 터널 스페이서를 갖는 완전 특징 고밀도 "전기적으로 소거 가능하고 프로그램 가능한 판독 전용 메모리(eeprom)" 셀을 제조하는 방법
US5885871A (en) Method of making EEPROM cell structure
EP0573728B1 (de) Verfahren zur Herstellung hochintegrierter kontaktloser EPROM's
US5637520A (en) Process for fabricating integrated devices including flash-EEPROM memories and transistors
US5051795A (en) EEPROM with trench-isolated bitlines
US6184554B1 (en) Memory cell with self-aligned floating gate and separate select gate, and fabrication process
US5385856A (en) Manufacture of the fieldless split-gate EPROM/Flash EPROM
US6043122A (en) Three-dimensional non-volatile memory
US5140551A (en) Non-volatile dynamic random access memory array and the method of fabricating thereof
JP3452522B2 (ja) 埋込み型ｎｖｒａｍアレイを有する集積回路チップの製造方法