ATE73580T1 - GATE ARRAY ARRANGEMENT USING CMOS TECHNOLOGY. - Google Patents

GATE ARRAY ARRANGEMENT USING CMOS TECHNOLOGY.

Info

Publication number
ATE73580T1
ATE73580T1 AT86116579T AT86116579T ATE73580T1 AT E73580 T1 ATE73580 T1 AT E73580T1 AT 86116579 T AT86116579 T AT 86116579T AT 86116579 T AT86116579 T AT 86116579T AT E73580 T1 ATE73580 T1 AT E73580T1
Authority
AT
Austria
Prior art keywords
fundamental
gate array
array arrangement
cmos technology
circuits
Prior art date
Application number
AT86116579T
Other languages
German (de)
Inventor
Heinz Peter Holzapfel
Petra Michel
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of ATE73580T1 publication Critical patent/ATE73580T1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/909—Microarchitecture
    • H10D84/935—Degree of specialisation for implementing specific functions
    • H10D84/937—Implementation of digital circuits
    • H10D84/938—Implementation of memory functions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

A gate array arrangement provides cell zones in the form of a matrix in a core zone of a chip. Each cell zone contains a fundamental circuit which consists of six or seven transistors designed in CMOS technology and which can perform a logic function or a storage function on the basis of appropriate interconnections. The connection of the fundamental circuits to one another is carried out either by way of the fundamental circuits or by using fundamental circuits which are not used to construct memories or logic functions. On the basis of the fundamental circuits consisting of six or seven n-channel and p-channel transistors it is possible to construct one storage cell per fundamental circuit and therefore to provide memories which can be adapted to the prevailing requirements in a gate array arrangement.
AT86116579T 1985-12-06 1986-11-28 GATE ARRAY ARRANGEMENT USING CMOS TECHNOLOGY. ATE73580T1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3543212 1985-12-06
EP86116579A EP0224887B1 (en) 1985-12-06 1986-11-28 Gate array arrangement using the cmos technique

Publications (1)

Publication Number Publication Date
ATE73580T1 true ATE73580T1 (en) 1992-03-15

Family

ID=6287843

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86116579T ATE73580T1 (en) 1985-12-06 1986-11-28 GATE ARRAY ARRANGEMENT USING CMOS TECHNOLOGY.

Country Status (7)

Country Link
US (1) US4779231A (en)
EP (1) EP0224887B1 (en)
JP (1) JPS62137843A (en)
KR (1) KR870006573A (en)
AT (1) ATE73580T1 (en)
CA (1) CA1273414A (en)
DE (1) DE3684249D1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821233A (en) * 1985-09-19 1989-04-11 Xilinx, Incorporated 5-transistor memory cell with known state on power-up
DE3714813A1 (en) * 1987-05-04 1988-11-17 Siemens Ag CMOS RAM STORAGE ON A GATE ARRAY ARRANGEMENT
NL194182C (en) * 1988-07-23 2001-08-03 Samsung Electronics Co Ltd Rimless master disk semiconductor device.
US5027319A (en) * 1988-09-02 1991-06-25 Motorola, Inc. Gate array macro cell
JPH0276197A (en) * 1988-09-13 1990-03-15 Toshiba Corp Semiconductor memory device
US5040146A (en) * 1989-04-21 1991-08-13 Siemens Aktiengesellschaft Static memory cell
US5898619A (en) * 1993-03-01 1999-04-27 Chang; Ko-Min Memory cell having a plural transistor transmission gate and method of formation
TW299448B (en) * 1995-07-20 1997-03-01 Matsushita Electric Industrial Co Ltd
US5831896A (en) * 1996-12-17 1998-11-03 International Business Machines Corporation Memory cell
DE102004059673B4 (en) 2004-12-10 2011-02-03 Infineon Technologies Ag System on chip, exposure mask arrangement and corresponding manufacturing method
US7321504B2 (en) * 2005-04-21 2008-01-22 Micron Technology, Inc Static random access memory cell
DE602006016537D1 (en) * 2005-11-25 2010-10-14 Semiconductor Energy Lab Operating method and arrangement of a semiconductor memory
US20150294738A1 (en) * 2014-04-15 2015-10-15 International Business Machines Corporation Test structure and method of testing a microchip

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3521242A (en) * 1967-05-02 1970-07-21 Rca Corp Complementary transistor write and ndro for memory cell
JPS57141097A (en) * 1981-02-25 1982-09-01 Toshiba Corp Storage circuit
JPS5864047A (en) * 1981-10-13 1983-04-16 Nec Corp Master-slice semiconductor integrated circuit device
JPS58119647A (en) * 1982-01-09 1983-07-16 Ricoh Co Ltd LSI master slice chip
JPS58139446A (en) * 1982-02-15 1983-08-18 Nec Corp Semiconductor integrated circuit device
DE3238311A1 (en) * 1982-10-15 1984-04-19 Siemens AG, 1000 Berlin und 8000 München Gate-array semiconductor integrated circuit
EP0119059B1 (en) * 1983-03-09 1988-10-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit with gate-array arrangement
EP0131463B1 (en) * 1983-07-09 1989-03-15 Fujitsu Limited Masterslice semiconductor device
JPS6047440A (en) * 1983-08-26 1985-03-14 Fujitsu Ltd Semiconductor integrated circuit
JPS6066447A (en) * 1983-09-21 1985-04-16 Nec Corp semiconductor integrated circuit
JPS6080251A (en) * 1983-10-08 1985-05-08 Fujitsu Ltd Gate array lsi device
JPS60179994A (en) * 1984-02-27 1985-09-13 Fujitsu Ltd Semiconductor memory device

Also Published As

Publication number Publication date
CA1273414A (en) 1990-08-28
EP0224887B1 (en) 1992-03-11
EP0224887A1 (en) 1987-06-10
DE3684249D1 (en) 1992-04-16
JPS62137843A (en) 1987-06-20
US4779231A (en) 1988-10-18
KR870006573A (en) 1987-07-13

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