ATE97258T1 - Verfahren zum herstellen einer integrierten schaltung mit mos-transistoren mittlerer spannung. - Google Patents

Verfahren zum herstellen einer integrierten schaltung mit mos-transistoren mittlerer spannung.

Info

Publication number
ATE97258T1
ATE97258T1 AT88420417T AT88420417T ATE97258T1 AT E97258 T1 ATE97258 T1 AT E97258T1 AT 88420417 T AT88420417 T AT 88420417T AT 88420417 T AT88420417 T AT 88420417T AT E97258 T1 ATE97258 T1 AT E97258T1
Authority
AT
Austria
Prior art keywords
making
integrated circuit
mos transistors
medium voltage
voltage mos
Prior art date
Application number
AT88420417T
Other languages
English (en)
Inventor
Philippe Boivin
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Application granted granted Critical
Publication of ATE97258T1 publication Critical patent/ATE97258T1/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0163Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including enhancement-mode IGFETs and depletion-mode IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/13Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
AT88420417T 1987-12-14 1988-12-14 Verfahren zum herstellen einer integrierten schaltung mit mos-transistoren mittlerer spannung. ATE97258T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8717782A FR2624653B1 (fr) 1987-12-14 1987-12-14 Procede de fabrication d'un circuit integre comprenant des transistors mos moyenne tension
EP88420417A EP0321366B1 (de) 1987-12-14 1988-12-14 Verfahren zum Herstellen einer integrierten Schaltung mit MOS-Transistoren mittlerer Spannung

Publications (1)

Publication Number Publication Date
ATE97258T1 true ATE97258T1 (de) 1993-11-15

Family

ID=9358075

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88420417T ATE97258T1 (de) 1987-12-14 1988-12-14 Verfahren zum herstellen einer integrierten schaltung mit mos-transistoren mittlerer spannung.

Country Status (6)

Country Link
EP (1) EP0321366B1 (de)
JP (1) JPH022171A (de)
KR (1) KR890011114A (de)
AT (1) ATE97258T1 (de)
DE (1) DE3885587T2 (de)
FR (1) FR2624653B1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3924062C2 (de) * 1989-07-21 1993-11-25 Eurosil Electronic Gmbh EEPROM-Halbleitereinrichtung mit Isolierzonen für Niedervolt-Logikelemente
JP3141446B2 (ja) * 1991-10-08 2001-03-05 日本電気株式会社 半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2123605A (en) * 1982-06-22 1984-02-01 Standard Microsyst Smc MOS integrated circuit structure and method for its fabrication
US4577394A (en) * 1984-10-01 1986-03-25 National Semiconductor Corporation Reduction of field oxide encroachment in MOS fabrication

Also Published As

Publication number Publication date
DE3885587T2 (de) 1994-06-16
FR2624653B1 (fr) 1991-10-11
EP0321366A1 (de) 1989-06-21
DE3885587D1 (de) 1993-12-16
KR890011114A (ko) 1989-08-12
FR2624653A1 (fr) 1989-06-16
EP0321366B1 (de) 1993-11-10
JPH022171A (ja) 1990-01-08

Similar Documents

Publication Publication Date Title
DE69012611D1 (de) Verfahren zum Herstellen bipolarer vertikaler Transistoren und von Hochspannungs-CMOS-Transistoren in einer einzigen integrierten Schaltung.
NO853699L (no) Tetralinderivater, fremstilling og anvendelse derav.
FI853622L (fi) Diarylacetylener, deras framstaellning och anvaendning.
DE3271346D1 (en) Method of making integrated bipolar transistors of very small dimensions
DE3576900D1 (de) Verfahren zum herstellen von gedruckten schaltungen.
DE3381215D1 (de) Integrierte halbleiterschaltungen und verfahren zur herstellung.
DE3586666D1 (de) Karte mit ic-baustein und verfahren zur herstellung derselben.
DE3881004D1 (de) Verfahren zum herstellen von integrierten cmos-anordnungen mit verringerten gate-laengen.
DE68913119D1 (de) Verfahren zum Betrieb einer MOS-Struktur und MOS-Struktur dafür.
DE3582556D1 (de) Verfahren zum herstellen von kontakten fuer integrierte schaltungen.
DE3850624D1 (de) Verfahren zum Herstellen von Halbleiterkontakten.
DE3681934D1 (de) Integrierter mos-transistor und verfahren zu seiner herstellung.
DE69107101D1 (de) Verfahren zum Herstellen eines Oxydfilms.
DE3685124D1 (de) Integriertes halbleiterschaltungsbauelement und verfahren zu seiner herstellung.
DE3682388D1 (de) Feldeffekttransistor verwendender schaltkreis und spannungsregler.
DE69029942D1 (de) Verfahren zur Herstellung von MOS-Leistungstransistoren mit vertikalem Strom
DE3861889D1 (de) Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen.
IT1210872B (it) Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.
FI822766A7 (fi) D-maitohapon valmistusmenetelmä Lactobacillus bulgaricus DSM 2129:n avulla.
DE3886062D1 (de) Verfahren zum Herstellen integrierter Strukturen aus bipolaren und CMOS-Transistoren.
DE3580025D1 (de) Halbleiter auf isolator-(soi)-anordnungen und verfahren zur herstellung von soi integrierten schaltungen.
PL264565A1 (en) Method of obtaining 6,7-substituted 1-cyclopropylo-1,4-dihydro-4-oxo-1,8-naphtirydino-3-carboxylic acids
DE3578266D1 (de) Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen.
DE3463882D1 (de) Mos-transistor amplifier
DE3484523D1 (de) Verfahren und mittel zur ausfuehrung einer prothese.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties