AU2004692A - Programmable interconnect structures and programmable integrated circuits - Google Patents

Programmable interconnect structures and programmable integrated circuits

Info

Publication number
AU2004692A
AU2004692A AU20046/92A AU2004692A AU2004692A AU 2004692 A AU2004692 A AU 2004692A AU 20046/92 A AU20046/92 A AU 20046/92A AU 2004692 A AU2004692 A AU 2004692A AU 2004692 A AU2004692 A AU 2004692A
Authority
AU
Australia
Prior art keywords
programmable
integrated circuits
interconnect structures
programmable interconnect
programmable integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU20046/92A
Other languages
English (en)
Inventor
Kathryn E Gordon
Richard J Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
QuickLogic Corp
Original Assignee
QuickLogic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by QuickLogic Corp filed Critical QuickLogic Corp
Publication of AU2004692A publication Critical patent/AU2004692A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
AU20046/92A 1991-04-26 1992-04-23 Programmable interconnect structures and programmable integrated circuits Abandoned AU2004692A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69195091A 1991-04-26 1991-04-26
US691950 1991-04-26

Publications (1)

Publication Number Publication Date
AU2004692A true AU2004692A (en) 1992-12-21

Family

ID=24778653

Family Applications (1)

Application Number Title Priority Date Filing Date
AU20046/92A Abandoned AU2004692A (en) 1991-04-26 1992-04-23 Programmable interconnect structures and programmable integrated circuits

Country Status (4)

Country Link
EP (1) EP0593529A4 (fr)
JP (1) JP3343251B2 (fr)
AU (1) AU2004692A (fr)
WO (1) WO1992020095A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475253A (en) * 1992-08-21 1995-12-12 Xilinx, Inc. Antifuse structure with increased breakdown at edges
US5387311A (en) * 1993-02-16 1995-02-07 Vlsi Technology, Inc. Method for manufacturing anti-fuse structures
DE4440539C2 (de) * 1994-11-12 1996-09-19 Itt Ind Gmbh Deutsche Programmierbarer Halbleiterspeicher
US5726484A (en) * 1996-03-06 1998-03-10 Xilinx, Inc. Multilayer amorphous silicon antifuse
DE10349749B3 (de) * 2003-10-23 2005-05-25 Infineon Technologies Ag Anti-Fuse-Verbindung für integrierte Schaltungen sowie Verfahren zur Herstellung von Anti-Fuse-Verbindungen
US7605410B2 (en) * 2006-02-23 2009-10-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20090115060A1 (en) 2007-11-01 2009-05-07 Infineon Technologies Ag Integrated circuit device and method
US11810854B2 (en) * 2019-05-15 2023-11-07 Tokyo Electron Limited Multi-dimensional vertical switching connections for connecting circuit elements

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720463A (en) * 1980-07-14 1982-02-02 Toshiba Corp Semiconductor memory device
US4519849A (en) * 1980-10-14 1985-05-28 Intel Corporation Method of making EPROM cell with reduced programming voltage
US4847732A (en) * 1983-09-15 1989-07-11 Mosaic Systems, Inc. Wafer and method of making same
US4666252A (en) * 1984-06-29 1987-05-19 Energy Conversion Devices, Inc. High yield liquid crystal display and method of making same
US4641420A (en) 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material

Also Published As

Publication number Publication date
EP0593529A4 (fr) 1995-03-22
JP3343251B2 (ja) 2002-11-11
JPH06509442A (ja) 1994-10-20
WO1992020095A1 (fr) 1992-11-12
EP0593529A1 (fr) 1994-04-27

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