AU427794B2 - Arrangement for providing a positive or a negative potential to an oup=tput or to a line etc in dependence on the level of an applied signal to an input - Google Patents

Description

3 8,215 72 The present invention relates to an arrangement for

providing a positive or a negative potential to an output

or to a line etc. in dependence on the level of an applied

signal to an input.

The object of the present invention is primarily to

achieve an alternative to current direction indicating

arrangements for example, so-called polarized relay circuits

of conventional type. Besides that the arrangement

according to the invention solves the problem with the function

itself, it complies with the demand of a simple construction,

free from maintenance, reability in operation, and at the same

time being considerably economic competitive compared with

arrangements known in the art.

What principally can be considered as characterizing

an arrangement according to the invention appears from the

characterizing part of the appended claims. The embodiments

which show the significant characteristics of the invention

till be described more in detail with reference to the

accompanying drawings in which:

Fig. I schematically shows a first embodiment;

Fig. 2 schematically shows a second embodiment and

Fig. 3 schematically shows a third embodiment of the invention.

In Fig.1 the input of the arrangement is indicated by

In and the output by Ut, furthermore a positive potential is

denoted by a and a negative potential is denoted by a

A first bistable element, consisting of a transistor T1 is

conncted between the positive potential and a reference

potential, which in the present embodiment is formed by earth

potential. The transistor T 1 is a npn-transistor the control

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/K (base) circuit of hich is 8,215 c /72 ected to a timing circuit

which in turn is connected to the input and consisting of a capacitor C in series with a resistorRI connected to earth potential. The base electrode of the transistor T is connected to the junction point A for the capacitor C

and' the resistor R I and the incoming signal is applied

to the base through the resistor R. Transistor T1 Is connected to earth potential through a voltage divider

R /R 2 3 and to the ositive potential through a collector resistor consisting of the resistors R4 and R where the 5 resistor R at the same time is the base resistor for a 4 further element consisting of a transistor T associated 2

with the transistor T i

Then the incoming signal- appears on the base of the .transistor T, with a positive level of a predetermined value, transistor T, ill conduct its main current by means of which it activates the further element, formed by the transistor T 2 which thereby is assumed to be saturated, whereupon the positive potential appears on the output Ut. The voltage divider R2/ 3 causes the predetermined positive value (threshold value) of the incoming signal.

Correspondingly a second bistable element formed by a pnp-transistor.T3 with an associated element in the form of a transistor T4 is connected between the negative potential and the earth potential. The base of transistor r3 is connected to the point A andtransistor T is connected to earth potential through a voltage divider R6/R 7 Upon an incoming negative signal on the base of the transistor

r3, this transistor is made conducting, the current through 'he resistor R and thus causing a saturation of the transistor T4 38,215/72 which implies that the output Ut will become negative. The voltage divider Rg/7 causes a predetermined threshold value for the negative incoming signal to saturate the transistor T3 and by a suitable dimensioning of the voltage dividers as well as of the timing circuit, one can assure that the transistors T 1 T3 and T 2 T4 respectively will not be conducting simultaneously, whereby a short circuit between the positive and the negative potentials is avoided. In the arrangement according to fig.1, the output Ut assumes a positive potential for a positive incoming signal and assumes a negative potential for a negative incoming signal, while it is zero-set in the absence of said signal.

In the arrangement according to fig. 2, on the other hand, transistor T1 is kept saturated and the positive potential appears on the output when the level of:.the incoming

signal is equal to zero while for a positive signal, transistor

TI', is blocked and transistor T is made conducting i.e. the output potential is changed from the positive to the negative

potential. Thisis :aused thereby that the incoming signal is applied to the base of a common-emitter-connected

transistor T, the collector resistance R10 to which the control circuits for the transistors T and T are connected. i

In the last mentioned control circuits two in series

connected resistors Ri and R12 are included, forming a voltage divider which is connected between the positive potential and the collector of transistor T 5 in a point D which is also earthed through a capacitor C' which operates

as the above mentioned timing circuit. Owing to the fact that the base of transistor T 1 is connected to the junction point B for the resistors Ri and Ri2. transistor T can

-4- be made conducting 3e rani, -T 5 isblocked, i.e. for example when the level of the incoming signal is zero, Upon a positive level of the incoming signal, transistor T 5 begins to conduct, the potential in point D thus decreases so much that the transistor Tit Is blocked* Upon the decreasing of the potential of the point D, transistor T3 obtains a base current, thus starting to conduct which in turn brings transistor T 4 to saturate. As long as the incoming signal remains in its positive level the output Ut is negative because of the saturating state of transistor T4 to

Fig. 3 shows an embodiment in which the input of the arrangement is isolated from Its output. In this case, the incoming signal is received through a conductor, (not shown)# to which the arrangement is connected via the Junctions points E and F. The inp ut of the arrangement shows two luminescent diodes Land L2which are connected in anti-parallel connection to the conductor through each zener diode Ziand Zresp ectiveJlyo Therewith it is assumed that the reverse voltage of the luminescent diodes exceeds the reverse voltage of the zener diodes* The zener diodes can be replaced by semi-conductors connected in the same direction-. as the respective luminescent diode. The zener diodes or the semi conductors cause the above mentioned threshold values for the incoming signal. In the inpout circuit is also, in- this case, included the mentioned timing circuit COAlt The luminescent diode LIs .adaDted to actuate a photo transistor T 1 1 forming said first bistable element and which Is arranged in the control circuit of*.a-trans istorT forming said further element, the collector of which is

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3 8 25 j d connected in series with a ftrther uminescent diode L3 which is connected to the output Ut. The luminescent diode L actuates in the corresponding manner the second 2 bistable element T which also consists of a photo transistor included in the control circuit of the further

element T which also consists of a transistor connected

in series with a further luminescent diode L 4 connected to

the output Ut. The luminescent diodes L 3 and L 4 cooperate with each a further photo transistor T 6 and T 7 respectively

included in the control circuits for the transistors T 2''

and T4 the luminescent diode L 3 activating the photo

transistor T 64for blocking the transistor T when transistor T 2 is conducting and the luminescent diode L 2 4. activating the photo diode T 7 for blocking the transistor

T2" when transistor T is conducting. The blocking operation is carried out thereby that the respective base-

emitter circuit for the transistor T 2 or T is being short circuited. For those cases rhen it is permitted that

the output voltage can be a feti volt lower than the feeding

voltage which is equal to the voltage between the positive

and the negative potentials, a current limiting circuit

consisting of a zener diode Z3 and a resistor R 1 3 is arranged

for the. transistor T 2 and a zener diode Z 4 and a resistor Itnito h 2 R. 14 is arranged for the transistor T The resistor and R-1 6 form blocking resistors for the transistors T and T "I.while the resistors R1 and R. form collector resistors

for the first and second element.T 1 l and T and atthe 3 same time they form the base resistors to -the transistors

T2 and T 2 4 Upon an incoming signal between the points E and P with

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38,215 f a level above the zener voltage of the zener diode Z 1 the

luminescent diode L, emits light thus activating the photo

transistor Ti'' This transistor in its turn, by means

of its collector current, influences the transistor T2

which is being saturated so that the positive potential

appears on the output Ut. The luminescent diode L 3 11 connected Ln series with the transistor T 2 emits light

and activates the photo transistor T 6 the emitter-collector

voltage of which consequently will exceed the zener voltage

of the zener diode Z4 which implies that the base-emitter

circuit of the transistor T 4 't will be short circuited. The

above mentioned operation is repeated for the corresponding

elements w:,hen the incoming signal with a negative level

exceeding the zener voltage in Z 2 appears between the points

E and F. The invention is not limited to the embodiments, the examples of which have been described above, but can be subject to modifications within the scope of the appended claims. As for example, the luminescent diodes in the arrangement according to fig. 3 can be exchanged for lamps. In the present arrangement, the blocking circuits L3P T6

and I T respectively can be omitted in dependence on "4 7 the requirements made on the circuit. Likewise, the potential divider in the form of the resistor R2/"3 and R 6 A 7 can be replaced by zener diodes.

Claims (3)

1. 3 8 2 15 in The claims defining the invention are as follows:-

   I An arrangement having an Input terminal and an output terminal for applying a positive or a negative potential to the output terminal in dependence on whether the value of an input signal exceeds a first predetermined level or underpasses a second predetermined level,, respect- ively, characterized in that a first electronic switching element, adapted to conduct a first main current is connected between said positive potential and a reference potential and that a second electronic switching element adapted to conduct a second main current Is connected between the reference potential and the negative potential, furthermore6 that control circuits associated with said switching elements are connected to the input terminal for sensing the level of said signal and. that the first element Is arranged to conduct its main current when said signal sensed by Its control circuit exceeds or Is equal to said first predetermined level and that the second element Is arranged to conduct its main current as said signal sensed by its control circuit is lower or is equal to said second predetermined level and that to-each of said switching elements a first and a second further element, respectively Is associated, said further elements being activated by means of said first and second currents, respectively., wherebjv said- positive and negative potential is applied to the output terminal.
2. 2. -Arn axi-rgement according to claim 1, characterized in that said first and second element consist of transistors and that each transist or is connected t6 the

   8- 4 27 794 a8,21 5 (12 reference potential through a voltage divider so dimensioned that the transistor in question will not be conducting until the incoming signal exceeds or underpasses the first or the second predetermined level respectively whereby the first transistor is prevented to conduct aiM- *ultaneously with the second transistor and vice versa.
3. 3. An arrangement according to claim 2, characterized In that a timing circuit is connected to said input terminal consisting of a capacitor connected to the reference potential in series with a res istor where said control circuits are connected to the Junction point between the capacitor and the resistor while the resistor Is connected to6 the input terminal..

   4. An arrangement according to claim 2, characterized In that to the input terminal a circuit is connected including a common-emitter connected transistor the collector resistor of which is connected to said control circuits including t.wo resistors connected in series and serving as a voltage divider and to the base of which the incoming signal Is transferred, the components being so dimensioned that said first element conducts when the inc- oming signal is zero and the second 6e-mrent conducts when the incoming signal is positive,

   Anl arrangement according to any one of the previous Iclaims, characterized in that said further elements consist of transistors and that these transistors are connected in series between the positive and the negatiVe potentials.

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   3 8,215 rn 6. An arrangement according to claim i,

   characterized in that the input terminal consists of

   two junction points between which a timing circuit is

   connected and that two luminescent diodes each are connected to one point of the timing circuit across a threshold value indicating means in the form of zener diodes or semiconductors, the two series connections thus obtained being connected in antiparallel.

   7. An arrangement according to claim 6, characterized in that the first and the second element consist. ofa photo transistor influenced by said luminescent diodes.

   8. An arrangement according to claim 6

   or claim 7, characterized in that the first and the second further elements in form of transistors each are connected in series with a further luminescent diode and that one of the luminescent diodes is connected in series with said first further element for activating a photo transistor included in a blocking circuit for said second further element and that the other of the luminescent diodes is connected in series with said second further element for activating a photo transistor included in a blocking circuit for said first further element.

   9. An arrangement according to claim 8, characterized in that said further elements are provided with current limitihg means. 2 DATED this17th day of August,197 TELEFONAKTIEBOLAGET L M1ERICSSON EDATD.WATERS SONS Russell Street MELBOURNE. VIC.

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