AU459130B2 - Circuit arrangement fora differential discriminator - Google Patents

Description

38,241 M

*7his invention relates to a circuit arrangement

for a differential-discriminator for adjusting the base line and the channel width of a comparator stage comprising two

comparators. Differential discriminators are used in the

radiation measurement technique as pulse level analysers

for quantitative spectrometrical measurements of high

accuracy. With their aid it is possible to select impulses

occurring within a given pulse height difference from a mixt-

ure of electric pulses of varying height which are emitted

from a detector and amplified by a linear amplifier. The

pulse height difference is limited by an adjustable lower

and an adjustable upper threshhold. The lower threshhold

is referred to as the base line, the distance of the upper

from the lower threshhold is referred to as channel width.

A base line comparator determines whether the pulses

delivered by the detector are situated above the lower thresh-

hold. A channel wid-th comparator determines whether the

pulses are situated below the upper threshhold. The pulses

wxhich are within the pulse height difference subsequently

X. release standardized rectangular pulses which reach an S average value measuring device or pulse counter in order

to obtain the impulse rate. Detectors which are used in the radiation measure-

ment technique are scintillation counters and proportional

counter tubes. Especially in X-ray fluorescence analysis

459.130

38,2 41 nz in which a detector picks up the x-ray fluorescence radiation

emitted from a sample which is radiated with X-ray light and in which the concentration of a chemical element contained

in the sample is determined by means of a connected differential discriminator, semiconductor detectors have

recently also been used, for instance lithium-drifted

silicon detectors. This type of semiconductor detector is able, in contrast to a proportional counter tube, to dissolve with sufficient accuracy the X-ray fluorescence radiation

emanating from chemical elements of adjacent specific atomic

number, to emit pulses whose levels differ sufficiently even when allowing for statistical inaccuracies.

Compared with this type of semiconductor detectors

the formerly employed differential discriminators have proved

unsuitable with regard to the time constancy of the base

line and to the channel width adjustment.

In the formerly employed circuit arrangements for differential discriminators the direct voltages required

for adjusting the base line and the channel width, i.e.,

the voltages required for adjusting the lower and the upper

threshhold of the pulse level difference, were conducted to

the base line or the channel width comparator via one or

several transistors. However, these transistor circuits are susceptible to temperature variations. The base-emitter volt- age of a silicon transistor, for instance, changes by about

mV at a temperature change of 10 C. At a channel width adjustment of 1V the effect of temperature on a single transistor during a temperature change of 10°C thus causes

a relative error cf 2.5% of the adjusted channel width. The temperature influence on the leakage current and on the current

-3 459130

38,241 /72 amplification of the transistor is not even taken into

account in this estiin't.e. With an adjusted channel width of 0.1 V the relative error caused by a temperature drift

of 10 C caused a relative error of as much as

It is the object of the invention to design a circuit arrangement for a differential discriminator of the above described type which ensures a far higher constancy of the base lines and channel widths adjustment than conventional

circuit arrangements. In accordance with the invention this task is solved in that a first highly constant and adjustable direct voltage is conducted to a first low-drift

impedance transformer having an output voltage which is proportional to this first direct voltage, that the first

direct voltage as well as a second highly constant and adjus- table direct voltage are supplied to a second low-drift

impedance transformer with an output voltage which is prop- ortional to the sum of the first and second direct voltages, and that the output voltage of the first impedance transformer is applied to the comparator input of the base line compar- ator whilst the output voltage of the second impedance

transformer is applied to the comparator input of the channel width comparator.

A particularly advantageous further development of the invention provides for the two impedance transformers

to be constructed in integrated technique as differential

amplifiers the voltage amplification of which, as a result

of reverse feedback, always equals one. In order to protect the channel width comparator against overloading it is

advisable that the positive supply voltage of the second

difference amplifier is selected substantially smaller than

4 459.130

38,241 rn the positive supply voltage of the first difference amplifier. It is also of advantage to take both adjustable

direct voltages from the same highly constant supply voltage

by potentiometer pick-off and/or to stabilize the supply voltage by means of a temperature compensated zener diode. Embodiments of the invention are described with

reference to.the attached drawings, in which:

Figure 1 illustrates a basic circuit arrangement

in the form of a block circuit diagram. Figure 2 is a detailed illustration of a circuit

arrangement with two differential amplifiers constructed in

integrated technique and

Figure 3 illustrates a differential-discriminator

using the circuit arrangement according to Figure 1. Figure 1 illustrates a circuit arrangement which

avoids inadmissibly high temperature faults of the adjustments

of base lines and of channel widths of a differential-discrimn-

ator. It is based on the consideration that the adjustable

direct voltages U 3 and U 4 which are applied to the comparat-

ive input of the base line comparator Kl and of the channel

width comparator K2 are to be obtained from low ohmic voltage

sources. A first highly constant and adjustable direct

voltage U 1 which is generally obtained from a high ohmic

voltage source (not illustrated) is conducted to a first

impedance transformer Il which is distinguished by a partic-

ularly small temperature dependent voltage fault. The output and voltage U 3 which is delivered to its low ohmic output

which is in proportion or equal to the first direct voltage line U 1 is applied to the comparative input of the base

5- 459 0

3 8,2 41 of comparator Kl. This ascertains whether the pulse level higher than the the test signal U S at the test input is direct voltage voltage U 3 which is adjusted by the first

U1 If this is the case, it supplies a voltage U 5 direct A second highly constant and adjustable

voltage U 2 which is also generally obtained from a high is supplied to a ohmic voltage source (not illustrated) low drift tendency. second impedance transformer 12. also of voltage U 1 At It also is supplied with the first direct voltage U 4 which its low ohmic output it delivers a discharge of the first and the is equal to or proportional to the sum second direct voltage U 1 and U 2 This output voltage U 4 and also by way which can be adjusted by way of the first is applied to the test of the second direct voltage U 1 or U 2 K2. The channel width input of the channel width comparator pulse level of the test comparator K2 ascertains whether the test input is smaller signal U S which is applied to its than the voltage U 4 If this is so, it provides a voltage the pulse level U It will be seen that in this circuit of the voltage U 4 remains difference which is adjusted by way altered. when the first direct voltage U 1 is of the invention Figure 2 represents an embodiment two low drift in which as impedance transformers Ii and 12

amplifiers Vl and V2 are utilized. Z with which A temperature compensated Zener diode in parallel is supplied two condensers Cl and C2 are arranged U via the resistance RO. by a stabilized supply voltage O resistors P1 and P2 and A series circuit of the adjustable parallel to the of the potentiometer P3 is also arranged

Zener diode Z. 6 459.130

38,241 n?2 The direct voltage UIwhich is obtained from the base line

potentiometer P3 is supplied to the first ampolifier VI via

resistor Ri. A series arrangement of the adjustable resist-

ors P4 and P5 and of the channel width potentiometer P6 is

also connected parallel to the Zener diode Z. The direct

voltage U2 which is obtained from the channel width potentio-

meter P6 is connected to the second amplifier V2 via

resistor R2. It will thus be seen that the two direct

voltages U 1I and U2 are obtained at the Zener diode Z from

the same highly constant component voltage of the same supply voltage U0

The amplifiers V1 and V2 which fulfil the tasks

of impedance transformers are galvanically coupled differen-

tial amplifiers which are preferably constructed in accord-

ance with integrated, monolithical technique and which are

arranged in a cormmon casing in accordance with dual-in-line

technique for the purpose of absorbing the same temperature.

Due to the reverse feedback with resistors Rl,

R3 and R2, R4 the voltage amplification of each of the two

amplifiers V1 or V2 equals one. The direct voltage U3 which

occurs at the output of amplifier V1 is therefore equal to direct voltage U1 when R1 R3. In addition to the direct

voltage U2 the input of amplifier V2 is also supplied with

the direct voltage U 1 whnich is obtained from the base line

potentiometer P3 and conducted via a resistor R5 (analogous

addition circuit), so that at its output there is available

as output voltage U 4 the sum of the direct voltages U 1 and

U2 adjusted at the potentiometers P3 and P6, when R5 R2

R4.

The output voltage U3 of the amplifier Vl is

7 45 9.13 0*

38,241 /2 conducted via the filter mermer comprising the resistor R6

and the condenser C3 to the reference input of the base

i- line comparator Kl. Similarly, the output voltage U 4 of the

'amplifier V2 is applied via the filter member comprising

Sresistor R7 and the condenser C4 at the reference input of

:the channel width comparator K2.

The test signal U S which comprises a mixture

of voltage pulses of different levels and which requires

Sanalysing; is-applied to a voltage divider comprising the

resistances R8 and R9. The signal which is obtained from

resistor R9 is conducted to the test inputs of the two

compaat rs I l and K2 via resistors R10 or R11. At the

output,if the base line comparator K1 a voltage U 5 appears

when -:he level of the pulse applied to its input is larger

than he voltage at its reference input which is adjusted

Svia the base line potentiometer P3, and at about the same

time an output voltage U6 occurs at theoutput of the channel

width comparator K2 when the impulse level is smaller than

the sum voltage at its reference input which is adjusted by

means of the base line potentiometer P3 and the channel width

potentiometer P6. The output voltages U 5 and U 6 are conducted

to a logical evaluation circuit of which the output signal

serves to release standardized rectangular pulses. As the temperature dependent voltage drift of

the conventional difference amplifiers V1 and V2, which are

constructed in accordance with integrated technique, only

amounts to a few micro volts per degree Celsius, and as the

temperature compensated Zener diode Z and the fixed and

control resistors used in the circuit arrangement possess

only a very small temperature coefficient, the direct voltages

8 459,13

38,2 41 M the comuaorators K(1 and applied to the reference inputs Of channel width of the K(2 for adjustinlg tbe base line and a negligibly small differential discriminator have only illustrated temp~erature fault. in the circuit arrangement that the voltage in Figure 2 it is further found of advantage at the channel width U4 for adjusting the channel width analogous addition comparator K(2 is the result of accurate are adj'Usted by of the direct voltages U 1 and U2which provides an exact link the potentiometers P3 and P6. This with the adjustment of the adjustment of the channel width width adjustment, of the base line. A continuous channel for the adjustment .of which may occur for instance, when sources are used which base line and channel width voltage avoided in the illustrated are independent of one another, is circuit arrangement. to Figure 2 In the circujit arrangement according discriminator K2 the destruction of the channel width the amplifier V2, which by the output direct voltage U4 of U and U2 which are corresponds to the sum of the voltages 1 P3 and the channel adjusted at the base line potentiometer when the input width potentiometer P6, can be prevented, circuit exceeds the permiss- voltage applied to its comparator the positive ;supply ible limit value. For this purpose is selected substantially voltage +UB2 of the amplifier V2 of the positive smaller i.e. half the magnitude, as that Vl. In contrast thereto supply voltage +UB1 of the amplifier and 2 are of identical the negative supply voltages _UB, usual commerical different- magnitude. To give an example of voltage U0 equals -24 V. ial amplifiers V1 and V2: The supply diode Z is -8.25 V, the the voltage obtained at the Zener 9 459.130

38,241 72 positive supply voltage +UB1 equals +12 V, the positive

supply voltage +UB 2 is +6 V, and the negative supply voltages

-UB1 and -UB2 each amountto -12 V. As a result of the vary-

ing selection of the positive supply voltages +Upi and +UB2 there occurs, when the permissible limit value is exceeded,

an automatic limitation of the output voltage U 4 of the

amplifier V2; thus providing a reliable protection against

overloading of the channel width discriminator K2.

Figure 3 represents the complete block circuit

of a differential discriminator comprising a comparator

stage consisting of two comparators K1 and K2. Here the

comparator stage is supplied with adjustable direct voltages

U 3 and U 4 of the circuit arrangement illustrated in Figure 1 in order to adjust an impulse height interval which is to

be examined.

The voltage pulses supplied by a-detector D enter

a linear amplifier G and from there reach the test input of

the base line comparator Kl and of the channel width compar-

ator K2 as test signal U S The base line adjustment is

effected by means of a direct voltage U 3 which is applied

to the comparator input of the baseline comparator K1 and is obtained from the adjustable direct voltage U 1 via the

low-drift impedance transformer Il. The adjustment of the

channel width at the channel width comparator K2 is effected

by means of a direct voltage U 4 which is formed from the

direct voltages U 1 and U 2 in the low-drift impedance trans-

former 12. If the pulse level of the test signal U S is

within the pulse level interval adjusted by the two thresh-

holds, output voltages U 5 or U6 occur at the outputs of

comparators K1 and K2 and are conducted to a logical evaluat- 10- 459.13

38,2 41 /2 ion circuit A. The pulses which are supplied from there

produce standardized rectangular pulses in an impulse

forming stage F which are amplified in an output amplifier

L and which are conducted via a switch S. They are collected as desired either in an average value tester M or in a

pulse counter Z.

n- 459.130

Claims (1)

1. 38,2 41 72 The claims defining the invention are as follows:

   1. A circuit arrangement for a differential-

   discriminator for adjusting the base line and the channel where- width of a comparator stage comprising two comparators

   in a test signal is applied to both the base line comparator

   and the channel width comparator, characterized in that a

   first highly constant and adjustable direct voltage is

   conducted to a first low-drift impedance transformer having

   an output voltage which is proportional to this first direct

   voltage, that the first direct voltage as well as a second

   highly constant and adjustable direct voltage are supplied

   to a second low-drift impedance transformer having an output

   voltage which is proportional to the sum of the first and

   second direct voltage and that the output voltage of the input first impedance transformer is applied to the comparator of of the base line comparator, whilst the output voltage

   the second impedance transformer is applied to the comparator

   input of the channel width compa'rator. 2. A circuit arrangement according to claim 1, are characterized in that the two impedance transformers

   difference amplifiers constructed in integrated technique, a result their voltage amplification always equalling one as of reverse coupling. 3. A circuit arrangement according to claim 2, of the characterized in that the positive supply voltage smaller second difference amplifier is selected substantially

   than the positive supply voltage of the first difference

   amplifier. 4. A circuit arrangement according to claim 1 in that the or any of the subsequent claims, characterized

   12- 459.130

   38,241 n7 two adjustable direct voltages are obtained by potentiometer

   pick-off from the same highly constant supply voltage. A circuit arrangement according to claim 4,

   characterized in that the supply voltage is stabilized by

   means of a temperature compensated Zener diode. 6. A circuit arrangement according to claim 2

   or any one of the subsequent claims, characterized in that s c'

   the two differential amplifiers are arranged closely along- L h side each other in order to achieve the same temperature f

   behaviour.

   DATED this TWENTIETH day of JANUARY 1972

   SIEMENS AKTIENGESELLSCHAFT

   Patent Attorneys for the Applicant SPRUSON FERGUSON

   S.,

   crr

   13 459.130

   ,38,241 /72

   Fig 1

   38,241 n2

   Fig. 2 81 j -uI-U

   9.1-3o

   38)241 172

   ft

   Fig. 3

   459,130