AU462000B2 - Circuit arrangement for synchronising ofthe line deflection ina television receiver - Google Patents

Description

41.489 /72 "Circuit arrangement for synchronising of the line deflect-

ion in a television receiver".

The invention relates to a circuit arrangement

for synchronising the line deflection in a television re-

ceiver in which a control voltage is obtained by comparison

of the phase position of the received synchronising pulses

relative to a sawtooth voltage derived from the line fly-

back pulses present in the receiver. In television receivers variations of the line

flyback pulses occur in practice, i.e. of the amplitude,

the shape (especially when an EHT transformer cooperating

with the line output stage is tuned to a so-called higher

harmonic) and the duration thereof. These variations may be

caused by tolerances in the transformer, variations of the

loads on the line output stage during the occurrence of the

pulses and of the load on the EHT generator. As a result

the phase position of the line deflection relative to the

received synchronising pulses varies so that the displayed

picture is locally shifted horizontally. In principle these

shifts may be compensated for.

Such a compensation circuit is, however, n:t

required if the edge of the sawtooth voltage which is com-

pared with the synchronising pulse is always located symme-

trically relative to the line flyback pulse. The line scan

then remains symmetrical with respect to the display screen.

To this end the circuit arrangement according to the inven-

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41.4 89 /72 tion is characterized in that the amplitude of the line flyback pulses is limited and that during the occurrence of said limited pulses a capacitor is discharged whose charge and/or discharge current is controlled in such a way that the mean value of the saw-tooth voltage produced across the capacitor is maintained substantially constant. In order that the invention may be readily carried into effect, an embodiment thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawing. In a television receiver not shown a terminal C receives a positively directed line flyback pulse.H whose edges and/or amplitude may be distorted. A potential divider comprising two resistors 1 and 2 is arranged between terminal C and earth and the junction of this divider is connected to the base of an npn-transistor 3. The emitter of transis- tor 3 is connected to earth. Potential divider 1, 2 is ad- justed in such a manner that a small part of the amplitude of pulse.H is already sufficient to bottom transistor 3. As a result a strong limitation occurs and the collector current of transistor 3 mainly corresponds to only the low part of pulse H. A voltage pulse is produced across the col- lector resistor 4 of transistor 3, which pulse is applied to the base of an npn-transistor 5 which also acts as a limited and whose emitter is connected to earth and whose collector is connected to the junction of two resistors 6

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and 7 and the base of an npn-transistor 8. Resistors 6 and

7 are arranged in series between the positive terminal of

a voltage supply source U and earth, while the negative

terminal of source U is connected to earth. The emitter

of transistor 8 is connected to earth through a resistor 9

and its collector is connected to earth through a capacitor

Resistors 6 and 7 are chosen to be such that capacitor

is discharged by a substantially constant current during

the period when transistor 5 is cut off during the occur-

rence of pulse H because transistor 3 is bottomed. Conse-

quently, the voltage across capacitor 10 decreases linearly

during the flyback period.

Capacitor 10 is also connected to the collector

of a pnp transistor 12 whose emitter is connected to the

positive terminal of source U and whose base is connected

to the collector of an npn-transistor 14. Collector resis-

tor 13 of transistor 14 is connected to the said positive

terminal while the emitter resistor 15 thereof is connected

to earth and the base is connected to the junction of two

resistors 16 and 17 which are arranged in series between

the two terminals of source U.

Furthermore the emitter of transistor 14 is

connected to the emitter of an npn-transistor 18 whose

collector is connected to the positive terminal of source

U and whose base is connected through a resistor 19 to

capacitor 10. Resistor 19 forms part of a smoothing filter

which includes, for example, also the series arrangement

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41.489 /72

20 arranged of a resistor 21 and a capacitor 22 and a capacitor direct voltage in parallel thereacross. As a result the mean applied to the component of the voltage across capacitor 10 is a diffe- base of transistor 18. Transistors 14 and 18 constitute is compared with rence amplifier by which the said direct voltage 17. The collector the voltage at the junction of resistors 16 and the difference current of transistor 14 is the output signal of 12. This amplifier, which signal drives the base of transistor 10. This transistor provides a current which charges capacitor 8 is cut off. is effected during the scan period when transistor Thus, due to the periodical charging and discharg- at the non- ing of capacitor 10 a sawtooth voltage is produced voltage which earthed terminal B thereof and the polarity of this In is applied to a phase comparison stage remains unchanged. discharging this stage the centre of the edge occurring during pulse of the sawtooth voltage is compared with the synchronising is so that the frequency and/or the phase of the line oscillator constantly re-adjusted in such a manner that the line deflection to the maintains a given position in known manner with respect synchronising pulse. If for some reason or other the duration of flyback period pulse H varies, the slope of the edge during the flyback comparison remains constant so that the adjustment of the phase stage and hence the position of the

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synchronising pulse with respect to the centre of pulse H does

not vary. It is true that the duration of the edge at terminal

B and hence also the peak-to-peak amplitude of the sawtooth volt- age varies. The mean value thereof is, however, maintained con-

stant by means of smoothing filter 19, 20, 21, 22 and transistor 18 so that only the slope of the sawtooth voltage at terminal B

will vary during charging of capacitor 10 and this part of the said voltage is not used for phase comparison. In the circuit arrangement described transistor 12

conducts when capacitor 10 is discharged so that due to its ad-

justment the discharge process of the capacitor is also influenced

by the adjustment of the transistor. This may be avoided with the

aid of the modification shown in broken lines. A resistor 25 is

arranged between the collector of transistor 3 and the base of

transistor 5 while the collector voltage of transistor 3 is applie

to the base of an npn-transistor 26, which transistor 26 is arrang

between resistor 15 and the emitters of transistors 14 and 18. W:hen pulse H occurs, the collector voltage of transistor 3 assumes

a very low value so that both transistor 5 and transistor 26 are

cut off. As a result transistors 14, 18 and 12 do not conduct

either. Thus, only transistor 8 is in the conducting state durinc

the flyback period and the discharge current of capacitor 10 is determined by this transistor only. In phase comparison stages not only a reference

voltage originating from the line output stage is

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41 489 /72

case a sawtooth voltage having generally required (in the relevant a reference voltage which corres- a constant mean value) but also voltage for the nominal phase. ponds to the value of the control the line oscillator are cor- As a result the phase and therefore absent. when synchronising pulses are rectly adjusted, for example, with vacuum tubes this voltage In ciruict arrangements equipped employing semiconductors, is often 0 V. Circuit arrangements require a reference voltage particularly in integrated circuits, 7 V battery voltage (for example, which is between P V and the 700). When the direct voltages employing the Philips type TAA the phase comparison stage, i.e. superimposed on the voltage of to the control voltage 0 V the direct voltage which corresponds control is produced when there is no and the direct voltage which pulses are absent) are voltage (for example, when synchronising with the aid of different poten- obtained for the battery voltage in the circuit arrangement may tial dividers, large asymmetries a may even be inadmissible. AS occur due to the tolerances and may vary and enter the non- result the oscillator frequency synchronised state. according An advantage of the circuit arrangement mean value at terminal B is deter- to the invention is that the the base of transistor 14 (ter- mined by the direct voltage at other uses throughout minal which voltage is available for tolerances caused by potential the period. The above-mentioned dividers are thus eliminated

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so that the phase comparison stage can be obtained with

a minimum of phase tolerances.

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Claims (1)

1. 41.489 /72 THE CLAIMS DEFINING THE INVENTION ARE A S FOLLOWS:

   Claim 1. A circuit arrangement for producing a saw- tooth voltage from line flyback pulses for the synchron- ization of a line time base stage in a television receiver in which a control voltage is obtained by com- parison of the phase position of received synchronising pulses relative to said sawtooth voltage, characterized i.n that the amplitude of the line flyback pulses is limited and that during the occurrence of said limited pulses a capacitor is discharged whose charge and/or discharge current is controlled in such a way that the mean value of the sawtooth voltage produced across the capacitor is. maintained substantially constant. Claim 2. A circuit arrangement as claimed in Claim 1, characterized in that the charge circuit of the capacitor includes a transistor which is driven by a difference am- plifier to which a fixed comparison voltage and the mean value of the sawtooth voltage are applied. Claim 3. A circuit arrangement as claimed in Claim-2, characterized in that the charge transistor is cut off during the occurrence of the line flyback pulses. Claim 4. A circuit arrangement as claimed in Claim 3, in which the difference amplifier consists of two emitter- coupled transistor, characterized in that the collector of a further transistor is connected to the two emitters,

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   which transistor is cut off by the limited pulses.

   A circuit arrangement for synchronising

   the line deflection in a television receiver, substanti-

   ally as herein described with reference to the accompany-

   ing drawing.

   Dated this twenty-first day of April, 1972

   N. V. PHILIPS' GLOEILAMPENFABRIEKEN

   10- 462. 000

   41. 489 /72

   L- -i

   A B

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