AU559558B2 - I/o channel bus - Google Patents

I/o channel bus

Info

Publication number
AU559558B2
AU559558B2 AU18222/83A AU1822283A AU559558B2 AU 559558 B2 AU559558 B2 AU 559558B2 AU 18222/83 A AU18222/83 A AU 18222/83A AU 1822283 A AU1822283 A AU 1822283A AU 559558 B2 AU559558 B2 AU 559558B2
Authority
AU
Australia
Prior art keywords
bus
data
register
signal
tag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU18222/83A
Other languages
English (en)
Other versions
AU1822283A (en
Inventor
K. Holly
G.J. Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elxsi
Original Assignee
Elxsi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/426,045 external-priority patent/US4564899A/en
Application filed by Elxsi filed Critical Elxsi
Publication of AU1822283A publication Critical patent/AU1822283A/en
Application granted granted Critical
Publication of AU559558B2 publication Critical patent/AU559558B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Traffic Control Systems (AREA)
AU18222/83A 1982-06-30 1983-06-29 I/o channel bus Ceased AU559558B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US39386082A 1982-06-30 1982-06-30
US393860 1982-06-30
US426045 1982-09-28
US06/426,045 US4564899A (en) 1982-09-28 1982-09-28 I/O Channel bus

Publications (2)

Publication Number Publication Date
AU1822283A AU1822283A (en) 1984-01-26
AU559558B2 true AU559558B2 (en) 1987-03-12

Family

ID=27014483

Family Applications (1)

Application Number Title Priority Date Filing Date
AU18222/83A Ceased AU559558B2 (en) 1982-06-30 1983-06-29 I/o channel bus

Country Status (3)

Country Link
EP (1) EP0112912A4 (de)
AU (1) AU559558B2 (de)
WO (1) WO1984000222A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4669056A (en) * 1984-07-31 1987-05-26 International Business Machines Corporation Data processing system with a plurality of processors accessing a common bus to interleaved storage
US6126945A (en) * 1989-10-03 2000-10-03 Pharmacia Ab Tumor killing effects of enterotoxins, superantigens, and related compounds
US5175825A (en) * 1990-02-02 1992-12-29 Auspex Systems, Inc. High speed, flexible source/destination data burst direct memory access controller
US5182800A (en) * 1990-11-16 1993-01-26 International Business Machines Corporation Direct memory access controller with adaptive pipelining and bus control features
EP0525233A1 (de) * 1991-07-30 1993-02-03 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren und Schaltungsanordnung für den Datenaustausch zwischen einer Leitungs- und einer Speicherseite durch direkte Speicherzugriffsübertragung
ATE165925T1 (de) * 1991-07-30 1998-05-15 Siemens Nixdorf Inf Syst Schaltungsanordnung zum aufbau gleichartiger peripheriegeräteanschlussschaltungen als zugangsschaltungen für unterschiedliche peripheriegeräte zu einem gemeinsamen bus
US5386532A (en) * 1991-12-30 1995-01-31 Sun Microsystems, Inc. Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810105A (en) * 1967-10-26 1974-05-07 Xerox Corp Computer input-output system
GB1314180A (en) * 1969-11-21 1973-04-18 Plessey Telecommunications Res Electrical data transmission systems
US3798613A (en) * 1971-10-27 1974-03-19 Ibm Controlling peripheral subsystems
US4038641A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Common polling logic for input/output interrupt or cycle steal data transfer requests
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4110830A (en) * 1977-07-05 1978-08-29 International Business Machines Corporation Channel storage adapter
US4246637A (en) * 1978-06-26 1981-01-20 International Business Machines Corporation Data processor input/output controller
AU518682B2 (en) * 1979-11-05 1981-10-15 Litton Resources Systems Inc. Computer system with direct access between peripheral devices
US4320457A (en) * 1980-02-04 1982-03-16 General Automation, Inc. Communication bus acquisition circuit

Also Published As

Publication number Publication date
AU1822283A (en) 1984-01-26
WO1984000222A1 (en) 1984-01-19
EP0112912A4 (de) 1987-04-28
EP0112912A1 (de) 1984-07-11

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