AU609284B2 - Data processing apparatus - Google Patents
Data processing apparatus Download PDFInfo
- Publication number
- AU609284B2 AU609284B2 AU33191/89A AU3319189A AU609284B2 AU 609284 B2 AU609284 B2 AU 609284B2 AU 33191/89 A AU33191/89 A AU 33191/89A AU 3319189 A AU3319189 A AU 3319189A AU 609284 B2 AU609284 B2 AU 609284B2
- Authority
- AU
- Australia
- Prior art keywords
- step counter
- segment
- data
- processing apparatus
- count
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
- Stored Programmes (AREA)
Description
609 2 4 ef: 93394 FORM COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATION
(ORIGINAL)
FOR OFFICE USE: Class Int Class Complete Specification Lodged: Accepted: Published: Priority: Related Art:
I
Name and Address of Applicant: NEC Corporation 33-1, Shiba Minato-ku Tokyo 108
JAPAN
Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Address for Service: Complete Specification for the invention entitled: Data Processing Apparatus The following statement is a full description of this invention, including the best method of performing it known to me/us REPRINT OF RECEIPT SOS0087 1 I 9'/0C4/e? j 5845/4 TO: THE COMMISSIONER OF PATENTS OUR REF: 93394 S&F CODE: 64259 ON ACCEPTED AND AMENDMIWNT f. 5845/3 Abstract of the Disclosure A data processing apparatus includes segment and page descriptors as a control structure for realizing a logical address, a step counter, and a count control means.
The step counter is incremented or decremented every time a machine instruction is executed. The count control means causes the step counter to count or stop counting in accordance with data in the segment or page descriptor of a segment or page in which a machine instruction to be '*ei executed is present.
t I I tL 4- t t i 44.4 f. a t
*A
4. The basic application referred to in paragraph 2 of this Declaration was/WbeY the first application made in a Convention country in respect of the invention the subject of the japplication.
)ec.lared at Tokyo, Japan this 23rd day of March, 1989.
NEC CORPORATION Sf' 1 i To: The Commissioner of Patents Signature of Declarant(s) 11/81 Susumu Uchihara General Manager, Patents Division y t.
N,'
Background of the Invention The present invention relates to count control of a step counter for a data processing apparatus.
Recently, as the application field of digital computers has been greatly extended, users' demands for functions have been diversified. Consequently, operating c systems for software have become very complicated. For this reason, structural analysis of an operating system cannot be S performed only by desk work. As a means for performing this C structural analysis, a step counter for counting a dynamic execution number of machine instructions is sometimes incorporated in a data processing apparatus.
t t V In such a conventional data processing apparatus, a step counter counts machine instructions in units of processes. However, since a program for software generally has a hierarchical structure using subroutines, when minute analysis such as structural analysis of a specific subroutine is to be performed, a count control instruction for causing a step counter to count or stop counting is inserted in the program for software in advance.
Since the above-described conventional step counter counts machine instructions in units of processes, when minute structural analysis is to be performed, a count control instruction for causing a step counter to count or stop counting must be inserted in a program for software in advance. Therefore, the conventional step counter has poor flexibility, and the processing speed is decreased.
Summary of the Invention The present invention has been made in consideration of the above situation, and has as its object to provide a data processing apparatus which can flexibly specify an object to be measured without degrading the performance of the apparatus.
S In order to achieve the above object, there is us..
*e provided a data processing apparatus including segment and 44Igtt page descriptors as a control structure for realizing a 4 1 logical address, comprising a step counter to be incremented 4 or decremented every time a machine instruction is executed, and count control means for causing the step counter to count or stop counting in accordance with data in the segment or page descriptor of a segment or page in which a machine instruction to be executed is present.
Brief Description of the Drawing Fig. 1 is a block diagram showing an arrangement of a data processing apparatus according to an embodiment of the present invention.
Detailed Description of the Preferred Embodiment Fig. 1 shows an arrangement of a data processing apparatus according to an embodiment of the present invention. Referring to Fig. i, reference numeral 1 denotes -2 i a logical address, 2, a segment descriptor; 3, a page descriptor; 4, a physical space; 5, a TLB (Translation Look-aside Buffer); 6, a flip-flop 7, an AND gate; and 8, a step counter (STPC).
1 The data processing apparatus of this embodiment comprises the segment and page descriptors 2 and 3 as a control structure for realizing the logical address 1.
Count control data 21 for causing the step counter 8 to count or stop counting is included in the segment descriptor 2.
Translation of the logical address 1 into a physical address is performed by an address translating 000000 1,0 section of the data processing apparatus through the control 0 0 structure constituted by a "table" consisting of the segment 0 and page descriptors 2 and 3 and the like which are present 0 in a main storage. The TLB 5 is arranged in the apparatus o: o in order to perform this translation at high speed.
The data 21 in the segment descriptor 2 is count control data for causing the step counter 8 to count or stop counting, and is stored in the TLB 5 as data 51. When "0 program read is performed in response to a program read 00 °signal a, the data 51 is stored in the flip-flop 6 and is supplied to the AND gate 7 as one input data b. When a machine instruction start signal c is supplied to the AND gate 7, if data stored in the flip-flop 6 is "ON" data, the step counter 8 is incremented or decremented. If the stored data is "OFF" data, incrementation or decrementation of the 3 Ai step counter 8 is not performed. Count control of the step counter 8 is performed by data in the segment descriptor 2 in this manner.
In this embodiment, count control data for causing the step counter 8 to count or stopping counting is present in the segment descriptor 2. However, the present invention can be equally applied to a case wherein this data is present in the page descriptor 3.
As has been described above, according to the 10 present invention, count control for causing a step counter a (which is incremented or decremented every time a machine 4 0 instruction is executed) to count or stop counting is performed by using data in a segment or page descriptor.
Therefore, an object to be measured can be flexibly specified, and the present invention can be easily used for, structural analysis of an operating system without degrading the performance of the apparatus.
4 4 4- I
Claims (1)
1. A data processing apparatus including segment and .2 page descriptors as a control structure for realizing a 3 logical address, comprising: 4 a step counter to be incremented or decremented every time a machine instruction is executed; and 6 count control means for causing said step counter 7 to count or stop counting in accordance with data in said 8 segment or page descriptor of a segment or page in which a 9 machine instruction to be executed is present. t DATED this EIGHTEENTH day of APRIL 1989 NEC Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-100249 | 1988-04-25 | ||
| JP63100249A JPH0831055B2 (en) | 1988-04-25 | 1988-04-25 | Data processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU3319189A AU3319189A (en) | 1989-10-26 |
| AU609284B2 true AU609284B2 (en) | 1991-04-26 |
Family
ID=14268955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU33191/89A Ceased AU609284B2 (en) | 1988-04-25 | 1989-04-19 | Data processing apparatus |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0831055B2 (en) |
| KR (1) | KR920003455B1 (en) |
| CN (1) | CN1010899B (en) |
| AU (1) | AU609284B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08292903A (en) * | 1995-04-21 | 1996-11-05 | Nec Corp | Information processor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0205122A2 (en) * | 1985-06-13 | 1986-12-17 | Tektronix, Inc. | Event counting prescaler |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136837A (en) * | 1983-12-26 | 1985-07-20 | Hitachi Ltd | Processing capacity evaluation method for computer systems |
-
1988
- 1988-04-25 JP JP63100249A patent/JPH0831055B2/en not_active Expired - Fee Related
-
1989
- 1989-04-19 AU AU33191/89A patent/AU609284B2/en not_active Ceased
- 1989-04-24 KR KR1019890005350A patent/KR920003455B1/en not_active Expired
- 1989-04-25 CN CN89102838A patent/CN1010899B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0205122A2 (en) * | 1985-06-13 | 1986-12-17 | Tektronix, Inc. | Event counting prescaler |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01273147A (en) | 1989-11-01 |
| CN1037415A (en) | 1989-11-22 |
| JPH0831055B2 (en) | 1996-03-27 |
| AU3319189A (en) | 1989-10-26 |
| KR890016479A (en) | 1989-11-29 |
| CN1010899B (en) | 1990-12-19 |
| KR920003455B1 (en) | 1992-05-01 |
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