BE1002653A4 - Circuit de conditionnement d'ecriture d'antememoire retarde pour un systeme de micro-calculateur a bus double comprenant une unite 80386 et une unite 82385. - Google Patents

Circuit de conditionnement d'ecriture d'antememoire retarde pour un systeme de micro-calculateur a bus double comprenant une unite 80386 et une unite 82385. Download PDF

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Publication number
BE1002653A4
BE1002653A4 BE8900440A BE8900440A BE1002653A4 BE 1002653 A4 BE1002653 A4 BE 1002653A4 BE 8900440 A BE8900440 A BE 8900440A BE 8900440 A BE8900440 A BE 8900440A BE 1002653 A4 BE1002653 A4 BE 1002653A4
Authority
BE
Belgium
Prior art keywords
unit
microculcor
antememory
delayed
writing
Prior art date
Application number
BE8900440A
Other languages
English (en)
Inventor
Ralph Murray Begun
Patrick Maurice Bland
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of BE1002653A4 publication Critical patent/BE1002653A4/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
  • Saccharide Compounds (AREA)
  • Microcomputers (AREA)

Abstract

Dans un système de micro-calculateur 80386/82385, les exigences de chronologie relatives aux éléments de mémoire sans possibilité d'antémémoire et placées par l'unité 82385 sont plus restrictives que les tolérances de chronologie placées sur les composants de mémoire sans possibilité d'antémémoire par l'unité 80386. La présente invention fonctionne sur les signaux de conditionnement d'écriture (CWE) d'antémémoire 82385 et retarde les signaux dans le cas d'une lecture manquée. Le retardement des signaux CWE élargit les tolérances de chronologie placée sur les composants de mémoire sans possibilité d'antémémoire et en même temps, n'affecte pas les paramètres d'état d'attente relatifs aux opérations de lecture manquée.
BE8900440A 1988-05-26 1989-04-20 Circuit de conditionnement d'ecriture d'antememoire retarde pour un systeme de micro-calculateur a bus double comprenant une unite 80386 et une unite 82385. BE1002653A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,890 US5175826A (en) 1988-05-26 1988-05-26 Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385

Publications (1)

Publication Number Publication Date
BE1002653A4 true BE1002653A4 (fr) 1991-04-23

Family

ID=22735299

Family Applications (1)

Application Number Title Priority Date Filing Date
BE8900440A BE1002653A4 (fr) 1988-05-26 1989-04-20 Circuit de conditionnement d'ecriture d'antememoire retarde pour un systeme de micro-calculateur a bus double comprenant une unite 80386 et une unite 82385.

Country Status (25)

Country Link
US (1) US5175826A (fr)
EP (1) EP0343989B1 (fr)
JP (1) JP2755330B2 (fr)
KR (1) KR930001584B1 (fr)
CN (1) CN1019151B (fr)
AT (1) ATE128566T1 (fr)
AU (1) AU615542B2 (fr)
BE (1) BE1002653A4 (fr)
BR (1) BR8902383A (fr)
CA (1) CA1314103C (fr)
CO (1) CO4520299A1 (fr)
DE (2) DE3911721A1 (fr)
DK (1) DK170677B1 (fr)
ES (1) ES2078237T3 (fr)
FI (1) FI96244C (fr)
FR (1) FR2632092A1 (fr)
GB (2) GB8904920D0 (fr)
HK (1) HK11592A (fr)
IT (1) IT1230208B (fr)
MX (1) MX170835B (fr)
MY (1) MY106968A (fr)
NL (1) NL8901327A (fr)
NO (1) NO175837C (fr)
SE (1) SE8901308L (fr)
SG (1) SG110991G (fr)

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US5586302A (en) * 1991-06-06 1996-12-17 International Business Machines Corporation Personal computer system having storage controller with memory write control
US5361368A (en) * 1991-09-05 1994-11-01 International Business Machines Corporation Cross interrogate synchronization mechanism including logic means and delay register
US5802548A (en) * 1991-10-25 1998-09-01 Chips And Technologies, Inc. Software programmable edge delay for SRAM write enable signals on dual purpose cache controllers
US5333276A (en) * 1991-12-27 1994-07-26 Intel Corporation Method and apparatus for priority selection of commands
US5309568A (en) * 1992-03-16 1994-05-03 Opti, Inc. Local bus design
US5426739A (en) * 1992-03-16 1995-06-20 Opti, Inc. Local bus - I/O Bus Computer Architecture
US5471585A (en) * 1992-09-17 1995-11-28 International Business Machines Corp. Personal computer system with input/output controller having serial/parallel ports and a feedback line indicating readiness of the ports
US6487626B2 (en) 1992-09-29 2002-11-26 Intel Corporaiton Method and apparatus of bus interface for a processor
US5898894A (en) 1992-09-29 1999-04-27 Intel Corporation CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval
US5613153A (en) * 1994-10-03 1997-03-18 International Business Machines Corporation Coherency and synchronization mechanisms for I/O channel controllers in a data processing system
US5890216A (en) * 1995-04-21 1999-03-30 International Business Machines Corporation Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
US6397295B1 (en) 1999-01-04 2002-05-28 Emc Corporation Cache mechanism for shared resources in a multibus data processing system
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
JP2005221731A (ja) * 2004-02-05 2005-08-18 Konica Minolta Photo Imaging Inc 撮像装置
US8996833B2 (en) * 2013-03-11 2015-03-31 Intel Corporation Multi latency configurable cache

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US4190885A (en) * 1977-12-22 1980-02-26 Honeywell Information Systems Inc. Out of store indicator for a cache store in test mode
US4171538A (en) * 1978-01-23 1979-10-16 Rockwell International Corporation Elastic store slip circuit apparatus for preventing read and write operations interference
US4189770A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Cache bypass control for operand fetches
JPS58169958A (ja) * 1982-03-31 1983-10-06 Fujitsu Ltd Ｍｉｓスタテイツク・ランダムアクセスメモリ
US4494190A (en) * 1982-05-12 1985-01-15 Honeywell Information Systems Inc. FIFO buffer to cache memory
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US4686621A (en) * 1983-06-30 1987-08-11 Honeywell Information Systems Inc. Test apparatus for testing a multilevel cache system with graceful degradation capability
JPH0795395B2 (ja) * 1984-02-13 1995-10-11 株式会社日立製作所 半導体集積回路
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EP0189944B1 (fr) * 1985-02-01 1993-05-12 Nec Corporation Circuit d'antémémoire capable de traiter une demande de lecture pendant le transfert d'un bloc de données
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JPS6261135A (ja) * 1985-09-11 1987-03-17 Nec Corp キヤツシユメモリ
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Title
ADVANCE INFORMATION, octobre 1988, Intel Corp., Santa Clara, US; "82385 High performance 32-bit cache controller" *
ELECTRONICS & WIRELESS WORLD, vol. 93, no. 1621, novembre 1987, pages 1121-1123, Sutton, Surrey, GB; D. JONES et al.: "The 68030" *
ELECTRONICS, vol. 60, no. 12, 11 novembre 1987, pages 74-76, New York, US; B.C. COLE: "How a cache control chip supercharges 386 processor" *

Also Published As

Publication number Publication date
CO4520299A1 (es) 1997-10-15
FI96244C (fi) 1996-05-27
DE3911721A1 (de) 1989-11-30
IT1230208B (it) 1991-10-18
HK11592A (en) 1992-02-21
MX170835B (es) 1993-09-20
NO175837C (no) 1994-12-14
AU615542B2 (en) 1991-10-03
NL8901327A (nl) 1989-12-18
MY106968A (en) 1995-08-30
FI96244B (fi) 1996-02-15
FI891788A0 (fi) 1989-04-14
EP0343989B1 (fr) 1995-09-27
DK189689D0 (da) 1989-04-19
KR930001584B1 (ko) 1993-03-05
CN1040104A (zh) 1990-02-28
AU3409689A (en) 1989-11-30
NO175837B (no) 1994-09-05
SE8901308D0 (sv) 1989-04-11
DK170677B1 (da) 1995-11-27
JPH0271344A (ja) 1990-03-09
US5175826A (en) 1992-12-29
EP0343989A2 (fr) 1989-11-29
GB8912019D0 (en) 1989-07-12
JP2755330B2 (ja) 1998-05-20
FI891788A7 (fi) 1989-11-27
NO891583D0 (no) 1989-04-18
GB8904920D0 (en) 1989-04-12
DE68924368T2 (de) 1996-05-02
SG110991G (en) 1992-02-14
FR2632092A1 (fr) 1989-12-01
NO891583L (no) 1989-11-27
ES2078237T3 (es) 1995-12-16
EP0343989A3 (fr) 1991-03-13
BR8902383A (pt) 1990-01-16
ATE128566T1 (de) 1995-10-15
IT8920649A0 (it) 1989-05-25
CN1019151B (zh) 1992-11-18
DE3911721C2 (fr) 1990-05-31
KR890017619A (ko) 1989-12-16
DE68924368D1 (de) 1995-11-02
GB2219111B (en) 1991-05-29
SE8901308L (sv) 1989-11-27
CA1314103C (fr) 1993-03-02
GB2219111A (en) 1989-11-29
DK189689A (da) 1989-11-27

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Date Code Title Description
RE Patent lapsed

Owner name: INTERNATIONAL BUSINESS MACHINES CORP.

Effective date: 19960430