BE621114A - - Google Patents
Info
- Publication number
- BE621114A BE621114A BE621114DA BE621114A BE 621114 A BE621114 A BE 621114A BE 621114D A BE621114D A BE 621114DA BE 621114 A BE621114 A BE 621114A
- Authority
- BE
- Belgium
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4921—Single digit adding or subtracting
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4924—Digit-parallel adding or subtracting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB29991/61A GB952118A (en) | 1961-08-19 | 1961-08-19 | Improvements relating to logical circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BE621114A true BE621114A (mo) |
Family
ID=10300486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BE621114D BE621114A (mo) | 1961-08-19 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US3229117A (mo) |
| BE (1) | BE621114A (mo) |
| DE (1) | DE1161312B (mo) |
| GB (1) | GB952118A (mo) |
| NL (1) | NL282229A (mo) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3309531A (en) * | 1964-03-04 | 1967-03-14 | Sylvania Electric Prod | Transistorized exclusive or logic circuit |
| US3303843A (en) * | 1964-04-20 | 1967-02-14 | Bunker Ramo | Amplifying circuit with controlled disabling means |
| US3569730A (en) * | 1967-10-23 | 1971-03-09 | Gen Signal Corp | Logic circuitry for railroad crossing systems |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3023965A (en) * | 1959-02-27 | 1962-03-06 | Burroughs Corp | Semi-conductor adder |
-
0
- NL NL282229D patent/NL282229A/xx unknown
- BE BE621114D patent/BE621114A/xx unknown
-
1961
- 1961-08-19 GB GB29991/61A patent/GB952118A/en not_active Expired
-
1962
- 1962-08-02 US US214372A patent/US3229117A/en not_active Expired - Lifetime
- 1962-08-09 DE DEA40911A patent/DE1161312B/de active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE1161312B (de) | 1964-01-16 |
| GB952118A (en) | 1964-03-11 |
| US3229117A (en) | 1966-01-11 |
| NL282229A (mo) |