BE748602A - Systeme de traitement de donnees a elements separes - Google Patents

Systeme de traitement de donnees a elements separes

Info

Publication number
BE748602A
BE748602A BE748602DA BE748602A BE 748602 A BE748602 A BE 748602A BE 748602D A BE748602D A BE 748602DA BE 748602 A BE748602 A BE 748602A
Authority
BE
Belgium
Prior art keywords
data processing
processing system
separate elements
separate
elements
Prior art date
Application number
Other languages
English (en)
French (fr)
Inventor
C H Schuenemann
W G Spruth
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19691922415 external-priority patent/DE1922415C3/de
Application filed by Ibm filed Critical Ibm
Publication of BE748602A publication Critical patent/BE748602A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Software Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
  • Multi Processors (AREA)
BE748602D 1969-05-02 1970-04-07 Systeme de traitement de donnees a elements separes BE748602A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19691922415 DE1922415C3 (de) 1969-05-02 Modulares elektronisches Datenverarbeitungssystem

Publications (1)

Publication Number Publication Date
BE748602A true BE748602A (fr) 1970-09-16

Family

ID=5733054

Family Applications (1)

Application Number Title Priority Date Filing Date
BE748602D BE748602A (fr) 1969-05-02 1970-04-07 Systeme de traitement de donnees a elements separes

Country Status (11)

Country Link
US (1) US3681761A (de)
JP (1) JPS5622019B1 (de)
AT (1) AT314225B (de)
BE (1) BE748602A (de)
CA (1) CA936966A (de)
CH (1) CH510302A (de)
ES (1) ES378182A1 (de)
FR (1) FR2046182A5 (de)
GB (1) GB1293442A (de)
NL (1) NL175348C (de)
SE (1) SE354365B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3939455A (en) * 1971-10-01 1976-02-17 Hitachi, Ltd. Microprocessor having an interface for connection of external devices
US3716843A (en) * 1971-12-08 1973-02-13 Sanders Associates Inc Modular signal processor
US3787817A (en) * 1972-06-21 1974-01-22 Us Navy Memory and logic module
US3790959A (en) * 1972-06-26 1974-02-05 Burroughs Corp Capacitive read only memory
US3936806A (en) * 1972-07-12 1976-02-03 Goodyear Aerospace Corporation Solid state associative processor organization
US3909789A (en) * 1972-11-24 1975-09-30 Honeywell Inf Systems Data processing apparatus incorporating a microprogrammed multifunctioned serial arithmetic unit
USRE30331E (en) * 1973-08-10 1980-07-08 Data General Corporation Data processing system having a unique CPU and memory timing relationship and data path configuration
DE2437252B1 (de) * 1974-08-02 1975-07-10 Ibm Deutschland Gmbh, 7000 Stuttgart Datenverarbeitungsanlage
US4085448A (en) * 1976-10-04 1978-04-18 International Business Machines Corporation Data communication bus structure
US4181941A (en) * 1978-03-27 1980-01-01 Godsey Ernest E Interrupt system and method
US4296469A (en) * 1978-11-17 1981-10-20 Motorola, Inc. Execution unit for data processor using segmented bus structure
US4268908A (en) * 1979-02-26 1981-05-19 International Business Machines Corporation Modular macroprocessing system comprising a microprocessor and an extendable number of programmed logic arrays
US4860379A (en) * 1979-05-18 1989-08-22 General Instrument Corporation Data communications system
FR2554255B1 (fr) * 1983-10-26 1985-12-27 Aerospatiale Dispositif electronique branche en parallele sur une ligne-bus et agencement comportant une pluralite de tels dispositifs
JPH03248226A (ja) * 1990-02-26 1991-11-06 Nec Corp マイクロプロセッサ
CN108363559B (zh) * 2018-02-13 2022-09-27 北京旷视科技有限公司 神经网络的乘法处理方法、设备和计算机可读介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL136144C (de) * 1959-10-19 1900-01-01
US3287703A (en) * 1962-12-04 1966-11-22 Westinghouse Electric Corp Computer
US3500328A (en) * 1966-06-20 1970-03-10 Ibm Data system microprogramming control
US3462742A (en) * 1966-12-21 1969-08-19 Rca Corp Computer system adapted to be constructed of large integrated circuit arrays
US3514758A (en) * 1967-03-27 1970-05-26 Burroughs Corp Digital computer system having multi-line control unit
US3537074A (en) * 1967-12-20 1970-10-27 Burroughs Corp Parallel operating array computer

Also Published As

Publication number Publication date
SE354365B (de) 1973-03-05
NL175348B (nl) 1984-05-16
GB1293442A (en) 1972-10-18
AT314225B (de) 1974-03-25
DE1922415B2 (de) 1973-02-01
CH510302A (de) 1971-07-15
US3681761A (en) 1972-08-01
CA936966A (en) 1973-11-13
NL175348C (nl) 1984-10-16
NL7005373A (de) 1970-11-04
FR2046182A5 (de) 1971-03-05
JPS5622019B1 (de) 1981-05-22
DE1922415A1 (de) 1970-11-05
ES378182A1 (es) 1972-05-16

Similar Documents

Publication Publication Date Title
BE823436A (fr) Systeme de traitement de donnees
BE753749A (fr) Systeme de traitement de donnees numeriques
FR2312072A1 (fr) Systeme de traitement de donnees
BE797619A (fr) Systeme perfectionne de traitement de donnes
FR2332572A1 (fr) Systeme de traitement des donnees
BE752718A (fr) Systeme d'exploration de donnees
FR2449310B1 (fr) Systeme de traitement de donnees a micro-programme
CH491440A (de) Datenverarbeitungsanlage
BE855477A (fr) Systeme de traitement de donnees
FR2329017A1 (fr) Systeme de traitement de donnees microprogramme
BE758721A (fr) Systeme automatise de traitement xerographique
CH532288A (de) Informationsverarbeitungsanlage
BE751250A (fr) Systeme de traitement de donnees comprenant plusieurs lignes dedonnees
BE758210A (fr) Systeme de lecture
AT303833B (de) Datenverarbeitungsanlage
BE745914A (fr) Systeme de transmission de donnees
BE770603A (fr) Systeme de traitement de donnees et lecteur pour
CH510302A (de) Elektronische Datenverarbeitungsanlage
BE757606A (fr) Systeme de traitement de donnees
BE763410A (fr) Systeme de traitement de donnees perfectionne a chevauchement des extractions
CH503324A (de) Datenverarbeitungsanlage
BE767720A (nl) Gegevens verwerkend stelsel
BE776987A (fr) Systeme de traitement de donnees
BE831871A (fr) Systeme de pistage de donnees de traitement
CH486738A (de) Datenverarbeitungsanlage

Legal Events

Date Code Title Description
RE20 Patent expired

Owner name: INTERNATIONAL BUSINESS MACHINES CORP.

Effective date: 19900407