BE750435A - Additionneur binaire parallele rapide - Google Patents

Additionneur binaire parallele rapide

Info

Publication number
BE750435A
BE750435A BE750435DA BE750435A BE 750435 A BE750435 A BE 750435A BE 750435D A BE750435D A BE 750435DA BE 750435 A BE750435 A BE 750435A
Authority
BE
Belgium
Prior art keywords
additioner
parallel binary
rapid parallel
rapid
binary
Prior art date
Application number
Other languages
English (en)
Inventor
L G Hanson
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of BE750435A publication Critical patent/BE750435A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
BE750435D 1969-07-22 1970-05-14 Additionneur binaire parallele rapide BE750435A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84352469A 1969-07-22 1969-07-22

Publications (1)

Publication Number Publication Date
BE750435A true BE750435A (fr) 1970-10-16

Family

ID=25290257

Family Applications (1)

Application Number Title Priority Date Filing Date
BE750435D BE750435A (fr) 1969-07-22 1970-05-14 Additionneur binaire parallele rapide

Country Status (7)

Country Link
US (1) US3697735A (fr)
JP (1) JPS5729738B1 (fr)
BE (1) BE750435A (fr)
CA (1) CA933662A (fr)
DE (1) DE2017132C3 (fr)
FR (1) FR2055238A5 (fr)
GB (1) GB1280392A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3805045A (en) * 1972-10-30 1974-04-16 Amdahl Corp Binary carry lookahead adder using redundancy terms
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
US4319335A (en) * 1979-10-16 1982-03-09 Burroughs Corporation Arithmetic logic unit controller
US4660165A (en) * 1984-04-03 1987-04-21 Trw Inc. Pyramid carry adder circuit
US4737926A (en) * 1986-01-21 1988-04-12 Intel Corporation Optimally partitioned regenerative carry lookahead adder
US4905180A (en) * 1988-12-16 1990-02-27 Intel Corporation MOS adder with minimum pass gates in carry line
EP0564137B1 (fr) * 1992-03-31 2001-06-20 STMicroelectronics, Inc. Soustracteur parallèlisé à retenue anticipée

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2879001A (en) * 1956-09-10 1959-03-24 Weinberger Arnold High-speed binary adder having simultaneous carry generation
US3440413A (en) * 1965-11-17 1969-04-22 Ibm Majority logic binary adder
US3440412A (en) * 1965-12-20 1969-04-22 Sylvania Electric Prod Transistor logic circuits employed in a high speed adder
US3465133A (en) * 1966-06-07 1969-09-02 North American Rockwell Carry or borrow system for arithmetic computations

Also Published As

Publication number Publication date
JPS5729738B1 (fr) 1982-06-24
CA933662A (en) 1973-09-11
DE2017132A1 (de) 1971-01-28
DE2017132C3 (de) 1980-02-07
GB1280392A (en) 1972-07-05
US3697735A (en) 1972-10-10
FR2055238A5 (fr) 1971-05-07
DE2017132B2 (de) 1979-06-07

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: BURROUGHS CORP.

Effective date: 19880531