BE751356A - Circuit resolveur de priorite pour echanges d'entree/sortie - Google Patents

Circuit resolveur de priorite pour echanges d'entree/sortie

Info

Publication number
BE751356A
BE751356A BE751356DA BE751356A BE 751356 A BE751356 A BE 751356A BE 751356D A BE751356D A BE 751356DA BE 751356 A BE751356 A BE 751356A
Authority
BE
Belgium
Prior art keywords
input
resolver circuit
priority resolver
output exchanges
exchanges
Prior art date
Application number
Other languages
English (en)
Inventor
E Balogh
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of BE751356A publication Critical patent/BE751356A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Telephonic Communication Services (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Exchange Systems With Centralized Control (AREA)
BE751356D 1969-07-09 1970-06-02 Circuit resolveur de priorite pour echanges d'entree/sortie BE751356A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84020869A 1969-07-09 1969-07-09

Publications (1)

Publication Number Publication Date
BE751356A true BE751356A (fr) 1970-11-16

Family

ID=25281726

Family Applications (1)

Application Number Title Priority Date Filing Date
BE751356D BE751356A (fr) 1969-07-09 1970-06-02 Circuit resolveur de priorite pour echanges d'entree/sortie

Country Status (6)

Country Link
US (1) US3638198A (fr)
JP (1) JPS5240176B1 (fr)
BE (1) BE751356A (fr)
DE (1) DE2025933C3 (fr)
FR (1) FR2054399A5 (fr)
GB (1) GB1255468A (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753014A (en) * 1971-03-15 1973-08-14 Burroughs Corp Fast inhibit gate with applications
DE2210426C2 (de) * 1972-03-03 1973-11-08 Nixdorf Computer Ag, 4790 Paderborn Verfahren zur vorranggesteuerten Auswahl einer von mehreren Funktions einheiten zur Anschaltung an eine ihnen gemeinsam zugeordnete Einrichtung in Datenverarbeitungsanlagen und Schaltung zur Durchführung des Verfahrens
US3812473A (en) * 1972-11-24 1974-05-21 Ibm Storage system with conflict-free multiple simultaneous access
US3815105A (en) * 1973-09-26 1974-06-04 Corning Glass Works Priority interrupt system
US3921145A (en) * 1973-10-12 1975-11-18 Burroughs Corp Multirequest grouping computer interface
US3984819A (en) * 1974-06-03 1976-10-05 Honeywell Inc. Data processing interconnection techniques
US4000487A (en) * 1975-03-26 1976-12-28 Honeywell Information Systems, Inc. Steering code generating apparatus for use in an input/output processing system
JPS5857836B2 (ja) * 1976-02-10 1983-12-22 ソニー株式会社 メモリ−装置
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4209839A (en) * 1978-06-16 1980-06-24 International Business Machines Corporation Shared synchronous memory multiprocessing arrangement
US4281381A (en) * 1979-05-14 1981-07-28 Bell Telephone Laboratories, Incorporated Distributed first-come first-served bus allocation apparatus
US4358829A (en) * 1980-04-14 1982-11-09 Sperry Corporation Dynamic rank ordered scheduling mechanism
US4597054A (en) * 1982-12-02 1986-06-24 Ncr Corporation Arbiter circuit and method
GB8702910D0 (en) * 1987-02-10 1987-03-18 British Telecomm Multi-user speech recognition system
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
AU2874089A (en) * 1988-01-28 1989-08-03 Interactive Engineering Pty. Ltd. Network connection mechanism
US5253343A (en) * 1988-08-18 1993-10-12 La Telemecanique Electric Method for the management of a memory of messages in a station of a data transmission network, and station designed for the implementation of the method
US5257382A (en) * 1988-09-19 1993-10-26 Unisys Corporation Data bank priority system
US5522080A (en) * 1991-10-24 1996-05-28 Intel Corporation Centralized control SIMD processor having different priority levels set for each data transfer request type and successively repeating the servicing of data transfer request in a predetermined order
JP2566719B2 (ja) * 1992-04-20 1996-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション データ通信インタフエース及びその動作方法
US5920403A (en) * 1995-10-09 1999-07-06 Konica Corporation Control method and control system for a copier

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3253262A (en) * 1960-12-30 1966-05-24 Bunker Ramo Data processing system
US3274554A (en) * 1961-02-15 1966-09-20 Burroughs Corp Computer system
US3307150A (en) * 1962-11-16 1967-02-28 Stromberg Carlson Corp Queue store
US3286240A (en) * 1962-12-31 1966-11-15 Ibm Channel status checking and switching system
US3449722A (en) * 1966-05-02 1969-06-10 Honeywell Inc Electronic multiprocessing apparatus including common queueing technique
US3449723A (en) * 1966-09-12 1969-06-10 Ibm Control system for interleave memory
FR1541240A (fr) * 1966-11-10 Ibm Accès à chevauchement et à intercalation pour mémoires à plusieurs vitesses

Also Published As

Publication number Publication date
US3638198A (en) 1972-01-25
JPS5240176B1 (fr) 1977-10-11
DE2025933B2 (de) 1973-11-29
FR2054399A5 (fr) 1971-04-16
DE2025933C3 (de) 1974-06-27
DE2025933A1 (de) 1971-01-21
GB1255468A (en) 1971-12-01

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: BURROUGHS CORP.

Effective date: 19880630