BE895065R - Additionneur binaire - Google Patents

Additionneur binaire

Info

Publication number
BE895065R
BE895065R BE2/59915A BE2059915A BE895065R BE 895065 R BE895065 R BE 895065R BE 2/59915 A BE2/59915 A BE 2/59915A BE 2059915 A BE2059915 A BE 2059915A BE 895065 R BE895065 R BE 895065R
Authority
BE
Belgium
Prior art keywords
binary adder
adder
binary
Prior art date
Application number
BE2/59915A
Other languages
English (en)
Inventor
C P H Lerouge
Original Assignee
Int Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Standard Electric Corp filed Critical Int Standard Electric Corp
Application granted granted Critical
Publication of BE895065R publication Critical patent/BE895065R/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
BE2/59915A 1981-11-19 1982-11-19 Additionneur binaire BE895065R (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8121656A FR2516675A1 (fr) 1981-11-19 1981-11-19 Cellule d'addition binaire a trois entrees a propagation rapide de la retenue

Publications (1)

Publication Number Publication Date
BE895065R true BE895065R (fr) 1983-05-19

Family

ID=9264158

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/59915A BE895065R (fr) 1981-11-19 1982-11-19 Additionneur binaire

Country Status (3)

Country Link
BE (1) BE895065R (fr)
FR (1) FR2516675A1 (fr)
GB (1) GB2113433A (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122946B1 (fr) * 1983-04-15 1987-09-09 Deutsche ITT Industries GmbH Additionneur binaire en CMOS
JPS60116034A (ja) * 1983-11-28 1985-06-22 Toshiba Corp 加算回路
FR2596544B1 (fr) * 1986-03-28 1988-05-13 Radiotechnique Compelec Circuit arithmetique et logique
EP0249789A1 (fr) * 1986-06-10 1987-12-23 Siemens Aktiengesellschaft Circuits de portes d'antivalence et d'équivalence

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147933A (en) * 1975-06-13 1976-12-18 Nippon Telegr & Teleph Corp <Ntt> Binary full adder circuit
JPS5360129A (en) * 1976-11-10 1978-05-30 Nippon Telegr & Teleph Corp <Ntt> Full adder circuit

Also Published As

Publication number Publication date
FR2516675A1 (fr) 1983-05-20
GB2113433A (en) 1983-08-03

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: ALCATEL N.V.

Effective date: 19880430