BE900156A - Procede pour superposer deux couches de vernis photosensibles positifs. - Google Patents

Procede pour superposer deux couches de vernis photosensibles positifs.

Info

Publication number
BE900156A
BE900156A BE2/60459A BE2060459A BE900156A BE 900156 A BE900156 A BE 900156A BE 2/60459 A BE2/60459 A BE 2/60459A BE 2060459 A BE2060459 A BE 2060459A BE 900156 A BE900156 A BE 900156A
Authority
BE
Belgium
Prior art keywords
superimposing
layers
positive photosensitive
photosensitive varnish
cooking operation
Prior art date
Application number
BE2/60459A
Other languages
English (en)
Inventor
D Beernaert
R Horre
Original Assignee
Itt Ind Belgium
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt Ind Belgium filed Critical Itt Ind Belgium
Priority to BE2/60459A priority Critical patent/BE900156A/fr
Publication of BE900156A publication Critical patent/BE900156A/fr
Priority to AU44270/85A priority patent/AU579161B2/en
Priority to EP85201166A priority patent/EP0171111A3/fr
Priority to JP60153900A priority patent/JPS6151923A/ja

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Materials For Photolithography (AREA)

Abstract

Un procédé pour superposer deux couches de vernis photosensibles positifs sur un dispositif semi-conducteur. Le procédé consiste à durcirs la surface supérieure de la première couche de vernis par une opération de cuisson, cette surface ayant été préalablement enduite d'une pellicule contenant du fluor obtenue lors d'une opération de cuisson dans un plasma contenant du fluor. Cette dernière opération de cuisson est généralement celle par laquelle la couche de polysilicium est gravée.
BE2/60459A 1984-07-13 1984-07-13 Procede pour superposer deux couches de vernis photosensibles positifs. BE900156A (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
BE2/60459A BE900156A (fr) 1984-07-13 1984-07-13 Procede pour superposer deux couches de vernis photosensibles positifs.
AU44270/85A AU579161B2 (en) 1984-07-13 1985-06-28 Process for superposing two photoresist layers
EP85201166A EP0171111A3 (fr) 1984-07-13 1985-07-11 Procédé pour la superposition de deux couches photoréserves
JP60153900A JPS6151923A (ja) 1984-07-13 1985-07-12 ２つのポジテイブフオトレジスト層を重ねる方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BE2/60459A BE900156A (fr) 1984-07-13 1984-07-13 Procede pour superposer deux couches de vernis photosensibles positifs.

Publications (1)

Publication Number Publication Date
BE900156A true BE900156A (fr) 1985-01-14

Family

ID=3865700

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/60459A BE900156A (fr) 1984-07-13 1984-07-13 Procede pour superposer deux couches de vernis photosensibles positifs.

Country Status (4)

Country Link
EP (1) EP0171111A3 (fr)
JP (1) JPS6151923A (fr)
AU (1) AU579161B2 (fr)
BE (1) BE900156A (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767721A (en) * 1986-02-10 1988-08-30 Hughes Aircraft Company Double layer photoresist process for well self-align and ion implantation masking
US5372914A (en) * 1992-03-24 1994-12-13 Kabushiki Kaisha Toshiba Pattern forming method
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8409457B2 (en) 2008-08-29 2013-04-02 Micron Technology, Inc. Methods of forming a photoresist-comprising pattern on a substrate
US8039399B2 (en) 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3131031A1 (de) * 1981-08-05 1983-02-24 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen der felddotierung beim herstellen von integrierten komplementaeren mos-feldeffekttransistoren
WO1986001313A1 (fr) * 1984-08-13 1986-02-27 Ncr Corporation Procede de formation d'une couche de protection photographique configuree

Also Published As

Publication number Publication date
AU579161B2 (en) 1988-11-17
JPS6151923A (ja) 1986-03-14
AU4427085A (en) 1986-01-16
EP0171111A2 (fr) 1986-02-12
EP0171111A3 (fr) 1987-07-22

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Legal Events

Date Code Title Description
CH Change of patent owner

Owner name: *BELL TELEPHONE MFG CY N.V.

Effective date: 19840713

RE Patent lapsed

Owner name: BELL TELEPHONE MFG CY N.V.

Effective date: 19870731