BR0012580A - Arquitetura de processador adaptada a linguagens de programa - Google Patents

Arquitetura de processador adaptada a linguagens de programa

Info

Publication number
BR0012580A
BR0012580A BR0012580-6A BR0012580A BR0012580A BR 0012580 A BR0012580 A BR 0012580A BR 0012580 A BR0012580 A BR 0012580A BR 0012580 A BR0012580 A BR 0012580A
Authority
BR
Brazil
Prior art keywords
processor architecture
instruction
program languages
data
program
Prior art date
Application number
BR0012580-6A
Other languages
English (en)
Inventor
Robert Tjornstroem
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR0012580A publication Critical patent/BR0012580A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/31—Programming languages or programming paradigms
    • G06F8/312—List processing, e.g. LISP programming language
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G06F12/0261—Garbage collection, i.e. reclamation of unreferenced memory using reference counting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/463—Program control block organisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

"ARQUITETURA DE PROCESSADOR ADAPTADA A LINGUAGENS DE PROGRAMA". Uma arquitetura de processador é adaptada a linguagens de programa, operando com um fluxo de instrução seq³encial e processando dados através do uso de listas ou tuplas ou tipos simples. Esta compreende um meio de manutenção de programa (1), um meio de manutenção de instrução (2,3), um meio de memória de dados (5) armazenando objetos de dados, e meio de execução (7). Os meios (4,5,6) são providos para processar referências a objetos de dados referenciados por vinculações e compreendendo meio (6) para incrementar contagens de referência para um objeto de dados e para decrementar contagens de referência para um objeto de dados, na dependência de uma instrução real a partir dos meios de manutenção de instrução (2,3).
BR0012580-6A 1999-07-21 2000-07-14 Arquitetura de processador adaptada a linguagens de programa BR0012580A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9902752A SE516171C2 (sv) 1999-07-21 1999-07-21 Processorarkitektur anpassas för programspråk med sekventiellt instruktionsflöde
PCT/SE2000/001494 WO2001006355A1 (en) 1999-07-21 2000-07-14 A processor architecture

Publications (1)

Publication Number Publication Date
BR0012580A true BR0012580A (pt) 2002-07-02

Family

ID=20416541

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0012580-6A BR0012580A (pt) 1999-07-21 2000-07-14 Arquitetura de processador adaptada a linguagens de programa

Country Status (8)

Country Link
EP (1) EP1208427B1 (pt)
JP (1) JP2003505758A (pt)
CN (1) CN1375083A (pt)
AU (1) AU6330500A (pt)
BR (1) BR0012580A (pt)
DE (1) DE60031136T2 (pt)
SE (1) SE516171C2 (pt)
WO (1) WO2001006355A1 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030097537A1 (en) * 2001-10-23 2003-05-22 Sun Microsystems, Inc. Method and apparatus for scoped memory
US8346810B2 (en) * 2011-05-13 2013-01-01 Simplivity Corporation Reference count propagation
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10114795B2 (en) * 2016-12-30 2018-10-30 Western Digital Technologies, Inc. Processor in non-volatile storage memory
JP6881256B2 (ja) * 2017-11-27 2021-06-02 オムロン株式会社 制御装置、制御方法、およびプログラム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922414A (en) * 1982-12-17 1990-05-01 Symbolics Inc. Symbolic language data processing system
US4695949A (en) * 1984-07-19 1987-09-22 Texas Instruments Incorporated Method for efficient support for reference counting
JP2501186B2 (ja) * 1985-07-04 1996-05-29 日本電気株式会社 デイジタル信号処理方法およびその装置
US4912629A (en) * 1986-06-26 1990-03-27 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Real-time garbage collection for list processing using restructured cells for increased reference counter size
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages
SE9002558D0 (sv) * 1990-08-02 1990-08-02 Carlstedt Elektronik Ab Processor
US5535390A (en) * 1994-07-22 1996-07-09 Hildebrandt; Thomas H. Method for reusing temporaries and reclaiming shared memory
WO1996008948A2 (en) * 1994-09-19 1996-03-28 Philips Electronics N.V. Method and apparatus for fast microcontroller context switching

Also Published As

Publication number Publication date
CN1375083A (zh) 2002-10-16
SE9902752L (sv) 2001-01-22
DE60031136T2 (de) 2007-08-16
SE516171C2 (sv) 2001-11-26
DE60031136D1 (de) 2006-11-16
AU6330500A (en) 2001-02-05
WO2001006355A1 (en) 2001-01-25
EP1208427B1 (en) 2006-10-04
EP1208427A1 (en) 2002-05-29
SE9902752D0 (sv) 1999-07-21
JP2003505758A (ja) 2003-02-12

Similar Documents

Publication Publication Date Title
DE60044752D1 (de) Verzweigungsbefehl für einen mehrfachverarbeitungsprozessor
BR9801230A (pt) Método de processador para transmissão de dados resultantes de instruções de armazenamento
BR0110751A (pt) Dispositivo
WO2001067237A3 (en) High-speed data processing using internal processor memory space
GB2413666B (en) Non main CPU/OS based operational environment
ES2143866T3 (es) Microprocesador multicadenas de mensajes conectados configurado para ejecutar rutinas de servicio de interruptor como una cadena de mensajes conectados.
DK0533781T3 (da) 3-aryl-2-hydroxypropionsyrederivater og -analoger som hypoglykæmiske midler
BR0207733A (pt) Processo para a regulação de um processo termodinâmico, especialmente de um processo de combustão
ITMI930578A1 (it) Metodo e dispositivo per salvare un'immagine di sistema su una memoria permanente, in modo indipendente dal sistema operativo
KR960035261A (ko) 적응성 인터럽트 맵핑 메카니즘 및 방법을 사용하는 다중처리 시스템
BR0209632A (pt) Método e sistema para instalação condicional e execução de serviços em um ambiente computacional seguro
DE3687724D1 (de) Digitalprozessorsteuerung.
BR9804697A (pt) Sistema de jogo operável com dados de backup em máquina de jogo do tipo diferente
BRPI0600196A (pt) ativação de dados de usuário final
BR0314853A (pt) Método e aparelho para manipulação de threads em um sistema de processamento de dados
ATE429673T1 (de) Dynamische bios-ausführung und gleichzeitiger update für einen blade-server
BRPI0703672A (pt) sistema e método para gerenciar interrupções de gerenciamento de sistema em um sistema de computador de multiprocessador
WO2004068271A3 (en) A reconfigurable semantic processor
BR0012580A (pt) Arquitetura de processador adaptada a linguagens de programa
BR0111950A (pt) Método e aparelho para proporcionar operação em tempo real em um sistema de computador pessoal
DE69739608D1 (de) Gastrechner-mikroprozessor mit vorrichtung zum zeitweisen anhalten des prozessorzustandes eines zielrechners
EP1089168A3 (en) Very long instruction word processor
BRPI0413175A (pt) aperfeiçoamento em identificação de animal
BR9810768A (pt) Processo de manuseio de instruções especìficas, e, processador
Broadey et al. Block-structured cross-referencers for Pascal and C.

Legal Events

Date Code Title Description
FA10 Dismissal: dismissal - article 33 of industrial property law
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired