BR0200649A - Aparelho de intercomunicação para um sistema duplex capaz de detectar falhas - Google Patents

Aparelho de intercomunicação para um sistema duplex capaz de detectar falhas

Info

Publication number
BR0200649A
BR0200649A BR0200649-9A BR0200649A BR0200649A BR 0200649 A BR0200649 A BR 0200649A BR 0200649 A BR0200649 A BR 0200649A BR 0200649 A BR0200649 A BR 0200649A
Authority
BR
Brazil
Prior art keywords
signal
parity
circuit
parallel
signals
Prior art date
Application number
BR0200649-9A
Other languages
English (en)
Inventor
Hirofumi Sudo
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of BR0200649A publication Critical patent/BR0200649A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)
  • Interconnected Communication Systems, Intercoms, And Interphones (AREA)

Abstract

"APARELHO DE INTERCOMUNICAçãO PARA UM SISTEMA DUPLEX CAPAZ DE DETECTAR FALHAS". Um circuito gerador de paridade 201 em um lado-O 20 recebe sinais de entrada s21 nas respectivas linhas de sinal e produz um bit de paridade p20 com base no sinal de entrada s21. Um circuito conversor paralelo/ serial 203 multiplexa sinais paralelos s22 (ou sinais de entrada s21) e o bit de paridade p20 dentro de um sinal serial s23 com referência a um sinal de sincronismo t20. Um circuito conversor serial/ paralelo 211 em um lado-1 21 reproduz sinais paralelos s24, sinal de paridade p21 e produz um sinal de verificação de sincronismo de paridade t21. Um circuito de verificação de paridade 212 verifica uma paridade de sinais paralelos s24 através do sinal de paridade p21. Se normal, um circuito mantenedor de estado 213 deverá manter saída s25 do circuito de verificação de paridade 212 como um sinal de estado. Se abnormal, o conteúdo mantido do circuito mantenedor de estado 213 será deletado.
BR0200649-9A 2001-02-23 2002-02-20 Aparelho de intercomunicação para um sistema duplex capaz de detectar falhas BR0200649A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001049361A JP2002251294A (ja) 2001-02-23 2001-02-23 ２重化交絡方式及び２重化交絡装置

Publications (1)

Publication Number Publication Date
BR0200649A true BR0200649A (pt) 2002-10-01

Family

ID=18910475

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0200649-9A BR0200649A (pt) 2001-02-23 2002-02-20 Aparelho de intercomunicação para um sistema duplex capaz de detectar falhas

Country Status (6)

Country Link
US (2) US7028242B2 (pt)
JP (1) JP2002251294A (pt)
CN (1) CN1177413C (pt)
AU (1) AU784712B2 (pt)
BR (1) BR0200649A (pt)
NZ (1) NZ517440A (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006285631A (ja) * 2005-03-31 2006-10-19 Yokogawa Electric Corp 二重化システム
CN108134880B (zh) * 2017-12-19 2019-09-24 中国电子科技集团公司第三十研究所 一种用户环路信令的快速检测方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1364264A (en) * 1970-11-16 1974-08-21 Sits Soc It Telecom Siemens Transmission system including a monitoring system
US3872257A (en) 1974-03-11 1975-03-18 Bell Telephone Labor Inc Multiplex and demultiplex apparatus for digital-type signals
US4250563A (en) * 1979-08-09 1981-02-10 Allen-Bradley Company Expandable programmable controller
JPS5753807A (en) * 1980-09-16 1982-03-31 Toshiba Corp Processsor of digital signal
JPS5753806A (en) * 1980-09-16 1982-03-31 Toshiba Corp Processor of digital signal
JPS5786137A (en) * 1980-11-18 1982-05-29 Sony Corp Pcm signal recording system
JPS5786118A (en) * 1980-11-18 1982-05-29 Sony Corp Pcm signal processing circuit
JPS6051312B2 (ja) * 1981-03-20 1985-11-13 日本ビクター株式会社 水平走査周波数逓倍回路
JPS59172836A (ja) 1983-03-23 1984-09-29 Hitachi Ltd 系切替信号伝達方式
AU567604B2 (en) * 1984-02-15 1987-11-26 Esselte Meto International Gmbh Method and system for detecting an indicating device
EP0348628A3 (en) * 1988-06-28 1991-01-02 International Business Machines Corporation Cache storage system
US4933930A (en) * 1988-10-31 1990-06-12 International Business Machines Corporation High speed switch as for an optical communication system
JP2762873B2 (ja) 1992-11-09 1998-06-04 日本電気株式会社 通話路系切り替え監視方式
JPH1011390A (ja) 1996-06-20 1998-01-16 Toshiba Corp マイクロプロセッサ応用装置
JP2000047892A (ja) 1998-07-30 2000-02-18 Nec Corp 交絡バス制御装置および交絡バス制御方法
US6188702B1 (en) 1998-11-17 2001-02-13 Inrange Technologies Corporation High speed linking module
US6233294B1 (en) 1999-08-17 2001-05-15 Richard Bowers Method and apparatus for accomplishing high bandwidth serial communication between semiconductor devices

Also Published As

Publication number Publication date
AU784712B2 (en) 2006-06-01
US7398447B2 (en) 2008-07-08
CN1372386A (zh) 2002-10-02
NZ517440A (en) 2004-03-26
AU1867802A (en) 2002-08-29
US20060156186A1 (en) 2006-07-13
JP2002251294A (ja) 2002-09-06
US7028242B2 (en) 2006-04-11
CN1177413C (zh) 2004-11-24
US20020120903A1 (en) 2002-08-29

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Legal Events

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B08L Patent application lapsed because of non payment of annual fee [chapter 8.12 patent gazette]

Free format text: REFERENTE AO NAO RECOLHIMENTO DAS 11A E 12A ANUIDADES.

B08I Publication cancelled [chapter 8.9 patent gazette]

Free format text: ANULADA A PUBLICACAO CODIGO 8.12 NA RPI NO 2257 DE 08/04/2014 POR TER SIDO INDEVIDA.

B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2602 DE 17-11-2020 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.