BR8202163A - Montagem de circuito projetada para alinhar uns a outros sinais concernentes a n feixes pom - Google Patents

Montagem de circuito projetada para alinhar uns a outros sinais concernentes a n feixes pom

Info

Publication number
BR8202163A
BR8202163A BR8202163A BR8202163A BR8202163A BR 8202163 A BR8202163 A BR 8202163A BR 8202163 A BR8202163 A BR 8202163A BR 8202163 A BR8202163 A BR 8202163A BR 8202163 A BR8202163 A BR 8202163A
Authority
BR
Brazil
Prior art keywords
pom
align
beams
circuit assembly
assembly designed
Prior art date
Application number
BR8202163A
Other languages
English (en)
Portuguese (pt)
Inventor
Vincenzo Falzone
Marcello Tommasi
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Publication of BR8202163A publication Critical patent/BR8202163A/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
BR8202163A 1981-04-30 1982-04-15 Montagem de circuito projetada para alinhar uns a outros sinais concernentes a n feixes pom BR8202163A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8121477A IT8121477A0 (it) 1981-04-30 1981-04-30 Disposizione circuitale atta ad allineare tra loro una pluralita'di fasci pcm coerenti che pervengono ad un nodo di comunicazione.

Publications (1)

Publication Number Publication Date
BR8202163A true BR8202163A (pt) 1983-03-29

Family

ID=11182405

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8202163A BR8202163A (pt) 1981-04-30 1982-04-15 Montagem de circuito projetada para alinhar uns a outros sinais concernentes a n feixes pom

Country Status (9)

Country Link
BR (1) BR8202163A (it)
DE (1) DE3216040A1 (it)
ES (1) ES511762A0 (it)
FR (1) FR2505108A1 (it)
GB (1) GB2102251A (it)
GR (1) GR76041B (it)
IT (1) IT8121477A0 (it)
PT (1) PT74815B (it)
YU (1) YU90982A (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2601534B1 (fr) * 1986-07-10 1993-07-30 Cit Alcatel Procede et dispositif de calage en phase de trains numeriques synchrones
CA2050650A1 (en) * 1990-11-28 1992-05-29 Shahrukh S. Merchant Phase aligner

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789775A (fr) * 1971-10-06 1973-04-06 Siemens Ag Dispositif de synchronisation mutuelle des oscillateurs de cadence de centraux d'un systeme de telecommunications pcm a multiplexage dans le temps
DE2247666C2 (de) * 1972-09-28 1975-02-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zur gegenseitigen Synchronisierung der In den Vermittlungsstellen eines PCM-Zeitmultlplex-FernmeMenetzes vorgesehenen Amtstaktoszillatoren
DE2641547C2 (de) * 1976-09-15 1980-11-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Übernahme von PCM Informationen
DE2936938C2 (de) * 1979-09-12 1987-01-08 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum Ausgleich der Phasenunterschiede zwischen dem Streckentakt auf einer mit einer PCM-Vermittlungsstelle verbindenden PCM-Zeitmultiplexleitung und dem Amtstakt dieser Vermittlungsstelle

Also Published As

Publication number Publication date
DE3216040A1 (de) 1982-11-25
ES8304391A1 (es) 1983-03-16
PT74815A (en) 1982-05-01
IT8121477A0 (it) 1981-04-30
PT74815B (en) 1983-11-30
GB2102251A (en) 1983-01-26
GR76041B (it) 1984-08-03
FR2505108A1 (fr) 1982-11-05
YU90982A (en) 1985-03-20
ES511762A0 (es) 1983-03-16

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