BR9703865A - Convers o de protocolo de sinalização entre um processador e um barramento de sistema de alta performance - Google Patents

Convers o de protocolo de sinalização entre um processador e um barramento de sistema de alta performance

Info

Publication number
BR9703865A
BR9703865A BR9703865A BR9703865A BR9703865A BR 9703865 A BR9703865 A BR 9703865A BR 9703865 A BR9703865 A BR 9703865A BR 9703865 A BR9703865 A BR 9703865A BR 9703865 A BR9703865 A BR 9703865A
Authority
BR
Brazil
Prior art keywords
conversion
processor
high performance
system bus
signaling protocol
Prior art date
Application number
BR9703865A
Other languages
English (en)
Inventor
James E Jacobson Jr
Michael W Rhodehamel
Matthew A Fisch
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9703865A publication Critical patent/BR9703865A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Small-Scale Networks (AREA)
BR9703865A 1996-07-03 1997-07-03 Convers o de protocolo de sinalização entre um processador e um barramento de sistema de alta performance BR9703865A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/675,679 US5845107A (en) 1996-07-03 1996-07-03 Signaling protocol conversion between a processor and a high-performance system bus

Publications (1)

Publication Number Publication Date
BR9703865A true BR9703865A (pt) 1998-09-08

Family

ID=24711535

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9703865A BR9703865A (pt) 1996-07-03 1997-07-03 Convers o de protocolo de sinalização entre um processador e um barramento de sistema de alta performance

Country Status (10)

Country Link
US (1) US5845107A (pt)
EP (1) EP0820020A3 (pt)
JP (1) JPH1139254A (pt)
KR (1) KR980010804A (pt)
CN (1) CN1176432A (pt)
AU (1) AU688718B2 (pt)
BR (1) BR9703865A (pt)
CA (1) CA2209157A1 (pt)
PL (1) PL185285B1 (pt)
TW (1) TW367445B (pt)

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US6330629B1 (en) * 1993-02-11 2001-12-11 Hitachi, Ltd. Information processing system
US5941972A (en) 1997-12-31 1999-08-24 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
USRE42761E1 (en) 1997-12-31 2011-09-27 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US6453377B1 (en) * 1998-06-16 2002-09-17 Micron Technology, Inc. Computer including optical interconnect, memory unit, and method of assembling a computer
KR20000059519A (ko) * 1999-03-04 2000-10-05 권상문 상호 다른 프로토콜을 이용하는 기종간의 통신시스템
US7136947B1 (en) * 1999-06-10 2006-11-14 Cadence Design Systems, Inc. System and method for automatically synthesizing interfaces between incompatible protocols
US6353867B1 (en) * 2000-01-14 2002-03-05 Insilicon Corporation Virtual component on-chip interface
US6658502B1 (en) * 2000-06-13 2003-12-02 Koninklijke Philips Electronics N.V. Multi-channel and multi-modal direct memory access controller for optimizing performance of host bus
US6346828B1 (en) 2000-06-30 2002-02-12 Intel Corporation Method and apparatus for pulsed clock tri-state control
KR100560761B1 (ko) * 2003-07-08 2006-03-13 삼성전자주식회사 인터페이스 변환 시스템 및 그 방법
KR100604835B1 (ko) * 2004-02-24 2006-07-26 삼성전자주식회사 프로토콜 변환중재회로, 이를 구비하는 시스템과 신호변환중재방법
CN100395745C (zh) * 2004-05-10 2008-06-18 联发科技股份有限公司 计算机系统以及外围装置的控制系统
US7328299B2 (en) * 2004-11-23 2008-02-05 Atmel Corporation Interface for compressed data transfer between host system and parallel data processing system
US10120663B2 (en) 2014-03-28 2018-11-06 Intel Corporation Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture

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US4727477A (en) * 1985-03-22 1988-02-23 International Business Machines Corp. Logically transportable microprocessor interface control unit permitting bus transfers with different but compatible other microprocessors
DE69020212T2 (de) * 1989-04-07 1996-04-04 Tektronix Inc Bus-zu-Bus Schnittstellensystem mit Konvertierung der Verriegelung.
US5060139A (en) * 1989-04-07 1991-10-22 Tektronix, Inc. Futurebus interrupt subsystem apparatus
DE3917715A1 (de) * 1989-05-31 1990-12-06 Teldix Gmbh Rechnersystem
IT1230238B (it) * 1989-06-08 1991-10-18 Bull Hn Information Syst Adattatore di interfaccia da vme a multibus ii.
US5297272A (en) * 1989-08-02 1994-03-22 Advanced Logic Research, Inc. Apparatus for automatically disabling and isolating a computer's original processor upon installation of a processor upgrade card
CA2051029C (en) * 1990-11-30 1996-11-05 Pradeep S. Sindhu Arbitration of packet switched busses, including busses for shared memory multiprocessors
US5255374A (en) * 1992-01-02 1993-10-19 International Business Machines Corporation Bus interface logic for computer system having dual bus architecture
US5551012A (en) * 1991-04-22 1996-08-27 Acer Incorporated Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip
EP0529142A1 (en) * 1991-08-30 1993-03-03 Acer Incorporated Upgradeable/downgradeable computers
US5412795A (en) * 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
JP2531903B2 (ja) * 1992-06-22 1996-09-04 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ・システムおよびシステム拡張装置
US5420985A (en) * 1992-07-28 1995-05-30 Texas Instruments Inc. Bus arbiter system and method utilizing hardware and software which is capable of operation in distributed mode or central mode
CA2099033A1 (en) * 1992-09-17 1994-03-18 Howard Thomas Olnowich Switch-based personal computer interconnection apparatus
US5490279A (en) * 1993-05-21 1996-02-06 Intel Corporation Method and apparatus for operating a single CPU computer system as a multiprocessor system
US5586270A (en) * 1993-09-30 1996-12-17 Intel Corporation Method and apparatus for upgrading a central processing unit and existing memory structure in a computer system
US5617546A (en) * 1993-12-22 1997-04-01 Acer Incorporated Data bus architecture compatible with 32-bit and 64-bit processors
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TW400483B (en) * 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US5623628A (en) * 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
AU1989395A (en) * 1994-03-14 1995-10-03 Apple Computer, Inc. A peripheral processor card for upgrading a computer
AU3143395A (en) * 1994-07-21 1996-02-22 Apple Computer, Inc. Method for semaphore communication between incompatible bus locking architectures
US5625802A (en) * 1994-12-12 1997-04-29 Digital Equipment Corporation Apparatus and method for adapting a computer system to different architectures
US5710891A (en) * 1995-03-31 1998-01-20 Sun Microsystems, Inc. Pipelined distributed bus arbitration system
US5644760A (en) * 1995-05-01 1997-07-01 Apple Computer, Inc. Printed circuit board processor card for upgrading a processor-based system

Also Published As

Publication number Publication date
EP0820020A3 (en) 1999-09-01
KR980010804A (ko) 1998-04-30
EP0820020A2 (en) 1998-01-21
TW367445B (en) 1999-08-21
PL185285B1 (pl) 2003-04-30
PL320929A1 (en) 1998-01-05
AU688718B2 (en) 1998-03-12
AU2837397A (en) 1998-01-15
US5845107A (en) 1998-12-01
JPH1139254A (ja) 1999-02-12
CN1176432A (zh) 1998-03-18
CA2209157A1 (en) 1998-01-03

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Legal Events

Date Code Title Description
FB34 Technical and formal requirements: requirement - article 34 of industrial property law
B11T Dismissal of application maintained [chapter 11.20 patent gazette]