BR9706408A - Método para junção multiplexada de saliências de solda em vários substratos durante montagem de pacote de circuito integrado e método para empacotar circuito integrado - Google Patents

Método para junção multiplexada de saliências de solda em vários substratos durante montagem de pacote de circuito integrado e método para empacotar circuito integrado

Info

Publication number
BR9706408A
BR9706408A BR9706408A BR9706408A BR9706408A BR 9706408 A BR9706408 A BR 9706408A BR 9706408 A BR9706408 A BR 9706408A BR 9706408 A BR9706408 A BR 9706408A BR 9706408 A BR9706408 A BR 9706408A
Authority
BR
Brazil
Prior art keywords
integrated circuit
multiplexing
joining
package assembly
various substrates
Prior art date
Application number
BR9706408A
Other languages
English (en)
Inventor
Stuart E Greer
David Clegg
Terry Edward Burnette
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of BR9706408A publication Critical patent/BR9706408A/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H05K3/3478—Application of solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
BR9706408A 1997-01-03 1997-12-18 Método para junção multiplexada de saliências de solda em vários substratos durante montagem de pacote de circuito integrado e método para empacotar circuito integrado BR9706408A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/775,981 US6117759A (en) 1997-01-03 1997-01-03 Method for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit package

Publications (1)

Publication Number Publication Date
BR9706408A true BR9706408A (pt) 1999-08-03

Family

ID=25106114

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9706408A BR9706408A (pt) 1997-01-03 1997-12-18 Método para junção multiplexada de saliências de solda em vários substratos durante montagem de pacote de circuito integrado e método para empacotar circuito integrado

Country Status (10)

Country Link
US (1) US6117759A (pt)
EP (1) EP0852395B1 (pt)
JP (1) JPH10209347A (pt)
KR (1) KR100470240B1 (pt)
CN (1) CN1128467C (pt)
BR (1) BR9706408A (pt)
DE (1) DE69711014T2 (pt)
MY (1) MY126386A (pt)
SG (1) SG71075A1 (pt)
TW (1) TW418473B (pt)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432744B1 (en) * 1997-11-20 2002-08-13 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
JP3798569B2 (ja) * 1999-02-23 2006-07-19 ローム株式会社 半導体装置の製造方法
US6333209B1 (en) * 1999-04-29 2001-12-25 International Business Machines Corporation One step method for curing and joining BGA solder balls
US6351393B1 (en) 1999-07-02 2002-02-26 International Business Machines Corporation Electronic package for electronic components and method of making same
US6373717B1 (en) 1999-07-02 2002-04-16 International Business Machines Corporation Electronic package with high density interconnect layer
JP3450236B2 (ja) * 1999-09-22 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6484927B1 (en) * 1999-11-05 2002-11-26 Delaware Capital Formation Corporation Method and apparatus for balling and assembling ball grid array and chip scale array packages
US6475828B1 (en) * 1999-11-10 2002-11-05 Lsi Logic Corporation Method of using both a non-filled flux underfill and a filled flux underfill to manufacture a flip-chip
JP3619410B2 (ja) * 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
TW498506B (en) * 2001-04-20 2002-08-11 Advanced Semiconductor Eng Flip-chip joint structure and the processing thereof
DE10133791B4 (de) * 2001-07-16 2007-04-19 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils
US6930032B2 (en) * 2002-05-14 2005-08-16 Freescale Semiconductor, Inc. Under bump metallurgy structural design for high reliability bumped packages
US7023707B2 (en) 2003-01-30 2006-04-04 Endicott Interconnect Technologies, Inc. Information handling system
US7035113B2 (en) 2003-01-30 2006-04-25 Endicott Interconnect Technologies, Inc. Multi-chip electronic package having laminate carrier and method of making same
CA2455024A1 (en) 2003-01-30 2004-07-30 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US20060068576A1 (en) * 2004-09-30 2006-03-30 Burdick William E Jr Lithography transfer for high density interconnect circuits
US7332818B2 (en) 2005-05-12 2008-02-19 Endicott Interconnect Technologies, Inc. Multi-chip electronic package with reduced line skew and circuitized substrate for use therein
KR101739742B1 (ko) * 2010-11-11 2017-05-25 삼성전자 주식회사 반도체 패키지 및 이를 포함하는 반도체 시스템
US8993378B2 (en) 2011-09-06 2015-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Flip-chip BGA assembly process
US9801285B2 (en) * 2012-03-20 2017-10-24 Alpha Assembly Solutions Inc. Solder preforms and solder alloy assembly methods
US9016552B2 (en) * 2013-03-15 2015-04-28 Sanmina Corporation Method for forming interposers and stacked memory devices
JP5874683B2 (ja) * 2013-05-16 2016-03-02 ソニー株式会社 実装基板の製造方法、および電子機器の製造方法
CN116209172A (zh) * 2022-05-23 2023-06-02 台达电子工业股份有限公司 电子模块的组装方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750665A (en) * 1986-11-21 1988-06-14 Indium Corporation Of America Method of producing a combination cover
FR2646558B1 (fr) * 1989-04-26 1994-04-01 Commissariat A Energie Atomique Procede et machine d'interconnexion de composants electriques par elements de soudure
US5188280A (en) * 1989-04-28 1993-02-23 Hitachi Ltd. Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals
US5313366A (en) * 1992-08-12 1994-05-17 International Business Machines Corporation Direct chip attach module (DCAM)
CA2135508C (en) * 1994-11-09 1998-11-03 Robert J. Lyn Method for forming solder balls on a semiconductor substrate
JP3563170B2 (ja) * 1995-09-08 2004-09-08 シチズン時計株式会社 半導体装置の製造方法
US5729896A (en) * 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder

Also Published As

Publication number Publication date
KR19980070272A (ko) 1998-10-26
EP0852395A3 (en) 1998-07-15
EP0852395B1 (en) 2002-03-13
MX9710068A (es) 1998-10-31
MY126386A (en) 2006-09-29
KR100470240B1 (ko) 2005-05-17
TW418473B (en) 2001-01-11
EP0852395A2 (en) 1998-07-08
CN1187030A (zh) 1998-07-08
DE69711014T2 (de) 2002-07-18
CN1128467C (zh) 2003-11-19
JPH10209347A (ja) 1998-08-07
US6117759A (en) 2000-09-12
DE69711014D1 (de) 2002-04-18
SG71075A1 (en) 2000-03-21

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Legal Events

Date Code Title Description
FA10 Dismissal: dismissal - article 33 of industrial property law
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]