BR9910563A - Lfsr de baixa potência - Google Patents

Lfsr de baixa potência

Info

Publication number
BR9910563A
BR9910563A BR9910563-2A BR9910563A BR9910563A BR 9910563 A BR9910563 A BR 9910563A BR 9910563 A BR9910563 A BR 9910563A BR 9910563 A BR9910563 A BR 9910563A
Authority
BR
Brazil
Prior art keywords
memory device
output terminal
shift operation
low power
feedback
Prior art date
Application number
BR9910563-2A
Other languages
English (en)
Inventor
Mattias Hansson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9910563A publication Critical patent/BR9910563A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Landscapes

  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Logic Circuits (AREA)
  • Acyclic And Carbocyclic Compounds In Medicinal Compositions (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

"LFSR DE BAIXA POTêNCIA" FSR de baixa potência compreendendo um conjunto ordenado de etapas de registrador incluindo meios de memória (1 - 7), caracterizado pelo fato dos meios de habilitação (F1 - F7, N1 - N7), habilitarem um único meio de memória (1 - 7) a cada operação de deslocamento. Cada etapa de registro compreende um meio de memória de baixa potência (7) consumindo um mínimo de energia quando está desabilitado, meios de retroalimentação (E7), um seu terminal de saída sendo conectado a um terminal de entrada do meio de memória (7), o meio de retroalimentação (E7) possuíndo primeiro e segundo terminais de entrada conectados a um terminal de saída (dado 7) do meio de memória (7) e um terminal de saída (dado2) de um segundo meio de memória subseq³ente (2), respectivamente, no conjunto. O terminal de saída (dado1 - dado7) de cada meio de memória (1 - 7) sendo conectado ao meio de seleção (M1), selecionando em cada operação de deslocamento o terminal de saída (dado1) de um primeiro meio de memória subseq³ente (1) em seguida ao corrente meio de memória (7) sendo habilitado na corrente operação de deslocamento.
BR9910563-2A 1998-05-18 1999-05-12 Lfsr de baixa potência BR9910563A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9801781A SE512009C2 (sv) 1998-05-18 1998-05-18 Linjärt återkopplade skiftregister med låg effekt
PCT/SE1999/000805 WO1999060574A1 (en) 1998-05-18 1999-05-12 Low power linear feedback shift registers

Publications (1)

Publication Number Publication Date
BR9910563A true BR9910563A (pt) 2001-01-30

Family

ID=20411391

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9910563-2A BR9910563A (pt) 1998-05-18 1999-05-12 Lfsr de baixa potência

Country Status (11)

Country Link
US (1) US6442579B1 (pt)
EP (1) EP1086468B1 (pt)
CN (1) CN1153224C (pt)
AT (1) ATE279008T1 (pt)
AU (1) AU4539299A (pt)
BR (1) BR9910563A (pt)
DE (1) DE69920907D1 (pt)
EE (1) EE03884B1 (pt)
MY (1) MY122206A (pt)
SE (1) SE512009C2 (pt)
WO (1) WO1999060574A1 (pt)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6691142B2 (en) * 2001-01-09 2004-02-10 Hewlett-Packard Development Company, L.P. Pseudo random address generator for 0.75M cache
US7136991B2 (en) * 2001-11-20 2006-11-14 Henry G Glenn Microprocessor including random number generator supporting operating system-independent multitasking operation
US7149764B2 (en) * 2002-11-21 2006-12-12 Ip-First, Llc Random number generator bit string filter
US20060064448A1 (en) * 2001-11-20 2006-03-23 Ip-First, Llc. Continuous multi-buffering random number generator
US7219112B2 (en) * 2001-11-20 2007-05-15 Ip-First, Llc Microprocessor with instruction translator for translating an instruction for storing random data bytes
US7139785B2 (en) * 2003-02-11 2006-11-21 Ip-First, Llc Apparatus and method for reducing sequential bit correlation in a random number generator
WO2005114415A2 (en) * 2004-05-11 2005-12-01 North Dakota State University Parallel architecture for low power linear feedback shift registers
US6961403B1 (en) * 2004-05-28 2005-11-01 International Business Machines Corporation Programmable frequency divider with symmetrical output
US8184034B2 (en) * 2008-07-21 2012-05-22 Cambridge Silicon Radio Limited Code sequence generator
US8949493B1 (en) 2010-07-30 2015-02-03 Altera Corporation Configurable multi-lane scrambler for flexible protocol support
US8299817B2 (en) * 2010-11-30 2012-10-30 Stmicroelectronics Asia Pacific Pte Ltd. Circuit and method for adding dither to vertical droop compensation using linear feedback shift registers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5974433A (en) * 1984-06-29 1999-10-26 Currie; Robert John High speed M-sequence generator and decoder circuit
JPH03214809A (ja) * 1990-01-19 1991-09-20 Nec Corp リニアフィードバック・シフトレジスタ
JPH0520887A (ja) * 1990-11-21 1993-01-29 Nippon Steel Corp シフト回路及びシフトレジスタ
US5867409A (en) * 1995-03-09 1999-02-02 Kabushiki Kaisha Toshiba Linear feedback shift register
JP3651154B2 (ja) * 1996-12-27 2005-05-25 ソニー株式会社 Ｐｎ符号発生回路及び無線システムの端末装置

Also Published As

Publication number Publication date
EP1086468B1 (en) 2004-10-06
EE200000661A (et) 2002-04-15
WO1999060574A1 (en) 1999-11-25
CN1301389A (zh) 2001-06-27
HK1038093A1 (en) 2002-03-01
EP1086468A1 (en) 2001-03-28
SE9801781L (sv) 1999-11-19
ATE279008T1 (de) 2004-10-15
DE69920907D1 (de) 2004-11-11
US6442579B1 (en) 2002-08-27
SE512009C2 (sv) 2000-01-10
AU4539299A (en) 1999-12-06
SE9801781D0 (sv) 1998-05-18
CN1153224C (zh) 2004-06-09
MY122206A (en) 2006-03-31
EE03884B1 (et) 2002-10-15

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A , 9A E 10A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO PUBLICADO NA RPI 1990 DE 25/02/2009.