BR9912705A - Ram chainback com cache para decodificador viterbi serial - Google Patents
Ram chainback com cache para decodificador viterbi serialInfo
- Publication number
- BR9912705A BR9912705A BR9912705-9A BR9912705A BR9912705A BR 9912705 A BR9912705 A BR 9912705A BR 9912705 A BR9912705 A BR 9912705A BR 9912705 A BR9912705 A BR 9912705A
- Authority
- BR
- Brazil
- Prior art keywords
- chainback
- cache
- block
- ram
- readings
- Prior art date
Links
- 238000000034 method Methods 0.000 abstract 5
- 238000005265 energy consumption Methods 0.000 abstract 1
- 238000005259 measurement Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Mobile Radio Communication Systems (AREA)
- Telephone Function (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Patente de Invenção: "RAM CHAINBACK COM CACHE PARA DECODIFICADOR VITERBI SERIAL". é provido um decodificador Viterbi serial possuindo uma cache chainback para uso em um telefone móvel. Em uma modalidade aqui descrita, o decodificador inclui um bloco de medida de erro de ramo, uma unidade de adicionar / comparar / selecionar e um bloco chainback incluindo uma RAM chainback, uma cache chainback completa e circuitos de controladores de chainback. A cache chainback acumula bits de decisão provenientes de ciclos de processo anteriores de tal forma que não seja necessário efetuar sempre operações completas de chainback. A cache chainback é configurada para acumular todas as leituras. Com a cache chainback podem ser conseguidas economias significativas no consumo de energia e no tempo de processamento, com um aumento relativamente modesto da quantidade de circuitos necessários. Em outra modalidade, não é provida uma cache chainback completa. Ao contrário, o bloco chainback inclui uma RAM de L+1 bits, um contador ascendente / descendente e um registrador de deslocamento configurado para emular uma cache chainback. Em mais outra modalidade, é empregado um registrador de deslocamento de L bits em lugar da combinação da RAM de L+1 bits e contador ascendente descendente. Nas várias modalidades, o bloco chainback pode ser configurado para efetuar somente uma leitura chainback em cada ciclo de processo, ou pode ser configurado para efetuar m leituras chainback em cada ciclo de processo. Em mais outras modalidades, o bloco chainback é configurado para efetuar operações chainback com base em leituras de a a b, em que a cache é acessada para cada leitura após a leituras terem sido feitas, até que b leituras tenham sido efetuadas ou seja obtida uma identidade. Em outras modalidades adicionais, o bloco chainback é configurado para efetuar operações chainback durante múltiplos ciclos de processo em lugar de apenas em um ciclo de processo.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/129,022 US6269130B1 (en) | 1998-08-04 | 1998-08-04 | Cached chainback RAM for serial viterbi decoder |
| PCT/US1999/017659 WO2000008769A1 (en) | 1998-08-04 | 1999-08-04 | Cached chainback ram for serial viterbi decoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BR9912705A true BR9912705A (pt) | 2002-01-15 |
Family
ID=22438110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR9912705-9A BR9912705A (pt) | 1998-08-04 | 1999-08-04 | Ram chainback com cache para decodificador viterbi serial |
Country Status (15)
| Country | Link |
|---|---|
| US (1) | US6269130B1 (pt) |
| EP (1) | EP1103101A1 (pt) |
| JP (1) | JP2002522944A (pt) |
| KR (1) | KR20010072210A (pt) |
| CN (1) | CN1164040C (pt) |
| AU (1) | AU763225B2 (pt) |
| BR (1) | BR9912705A (pt) |
| CA (1) | CA2339257A1 (pt) |
| ID (1) | ID28514A (pt) |
| IL (1) | IL141228A0 (pt) |
| NZ (1) | NZ509695A (pt) |
| RU (1) | RU2236084C2 (pt) |
| UA (1) | UA75863C2 (pt) |
| WO (1) | WO2000008769A1 (pt) |
| ZA (1) | ZA200100914B (pt) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6463031B1 (en) * | 1998-12-03 | 2002-10-08 | Nokia Mobile Phones Limited | Rate determination technique that utilizes modified cumulative metrics to orthogonalize the rates |
| JP3399414B2 (ja) * | 1999-09-14 | 2003-04-21 | 日本電気株式会社 | 送受信回路及びそれを用いた移動通信端末装置並びにその制御方法及びその制御プログラム記録媒体 |
| US6757864B1 (en) * | 2000-04-06 | 2004-06-29 | Qualcomm, Incorporated | Method and apparatus for efficiently reading and storing state metrics in memory for high-speed ACS viterbi decoder implementations |
| US7359464B2 (en) * | 2003-12-31 | 2008-04-15 | Intel Corporation | Trellis decoder and method of decoding |
| US7716551B2 (en) * | 2005-12-07 | 2010-05-11 | Microsoft Corporation | Feedback and frame synchronization between media encoders and decoders |
| KR20110124729A (ko) * | 2010-05-11 | 2011-11-17 | 한국전자통신연구원 | 통신 시스템에서 데이터 송수신 장치 및 방법 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4240156A (en) * | 1979-03-29 | 1980-12-16 | Doland George D | Concatenated error correcting system |
| US4979175A (en) * | 1988-07-05 | 1990-12-18 | Motorola, Inc. | State metric memory arrangement for a viterbi decoder |
| US5408502A (en) * | 1992-07-13 | 1995-04-18 | General Instrument Corporation | Apparatus and method for communicating digital data using trellis coded QAM with punctured convolutional codes |
| KR960011125B1 (ko) * | 1993-01-30 | 1996-08-20 | 삼성전자 주식회사 | 시분할 다중 통신 채널용 디지탈 복조 회로 |
| ZA947317B (en) * | 1993-09-24 | 1995-05-10 | Qualcomm Inc | Multirate serial viterbi decoder for code division multiple access system applications |
| US6005898A (en) * | 1997-03-12 | 1999-12-21 | Interdigital Technology Corporation | Multichannel viterbi decoder |
| US6094465A (en) * | 1997-03-21 | 2000-07-25 | Qualcomm Incorporated | Method and apparatus for performing decoding of CRC outer concatenated codes |
| US6038269A (en) * | 1997-11-20 | 2000-03-14 | National Semiconductor Corporation | Detection for digital communication receivers |
-
1998
- 1998-08-04 US US09/129,022 patent/US6269130B1/en not_active Expired - Lifetime
-
1999
- 1999-04-08 UA UA2001010727A patent/UA75863C2/uk unknown
- 1999-08-04 CA CA002339257A patent/CA2339257A1/en not_active Abandoned
- 1999-08-04 KR KR1020017001439A patent/KR20010072210A/ko not_active Ceased
- 1999-08-04 JP JP2000564306A patent/JP2002522944A/ja active Pending
- 1999-08-04 RU RU2001105943/09A patent/RU2236084C2/ru not_active IP Right Cessation
- 1999-08-04 AU AU53357/99A patent/AU763225B2/en not_active Ceased
- 1999-08-04 IL IL14122899A patent/IL141228A0/xx not_active IP Right Cessation
- 1999-08-04 NZ NZ509695A patent/NZ509695A/xx not_active IP Right Cessation
- 1999-08-04 EP EP99938987A patent/EP1103101A1/en not_active Withdrawn
- 1999-08-04 WO PCT/US1999/017659 patent/WO2000008769A1/en not_active Ceased
- 1999-08-04 CN CNB998116564A patent/CN1164040C/zh not_active Expired - Lifetime
- 1999-08-04 BR BR9912705-9A patent/BR9912705A/pt not_active IP Right Cessation
- 1999-08-04 ID IDW20010538A patent/ID28514A/id unknown
-
2001
- 2001-02-01 ZA ZA200100914A patent/ZA200100914B/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CA2339257A1 (en) | 2000-02-17 |
| RU2236084C2 (ru) | 2004-09-10 |
| ID28514A (id) | 2001-05-31 |
| CN1321363A (zh) | 2001-11-07 |
| JP2002522944A (ja) | 2002-07-23 |
| WO2000008769A1 (en) | 2000-02-17 |
| CN1164040C (zh) | 2004-08-25 |
| US6269130B1 (en) | 2001-07-31 |
| AU763225B2 (en) | 2003-07-17 |
| ZA200100914B (en) | 2002-05-02 |
| KR20010072210A (ko) | 2001-07-31 |
| EP1103101A1 (en) | 2001-05-30 |
| HK1038449A1 (en) | 2002-03-15 |
| NZ509695A (en) | 2002-08-28 |
| IL141228A0 (en) | 2002-03-10 |
| UA75863C2 (en) | 2006-06-15 |
| AU5335799A (en) | 2000-02-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B08F | Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette] |
Free format text: REFERENTE A 8O E 9O ANUIDADES. |
|
| B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |
Free format text: REFERENTE AO DESPACHO 8.6 DA RPI 1999 DE 28/04/2009. |