BRPI0409107A - loop travado por fase digital - Google Patents

loop travado por fase digital

Info

Publication number
BRPI0409107A
BRPI0409107A BRPI0409107-8A BRPI0409107A BRPI0409107A BR PI0409107 A BRPI0409107 A BR PI0409107A BR PI0409107 A BRPI0409107 A BR PI0409107A BR PI0409107 A BRPI0409107 A BR PI0409107A
Authority
BR
Brazil
Prior art keywords
pfd
adaptive
idac
phase
provides
Prior art date
Application number
BRPI0409107-8A
Other languages
English (en)
Inventor
Amr Fahim
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0409107A publication Critical patent/BRPI0409107A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

"LOOP TRAVADO POR FASE DIGITAL". Um PLL digital inclui um PFD adaptativo, um filtro de loop adaptativo, um iDAC, um ICO e um divisor. O PFD adaptativo recebe um sinal de referência e um sinal de realimentação, determina erro de fase entre os dois sinais, e provê um valor PFD para cada período de comparação de fase. A magnitude do valor PFD é ajustada para se obter rápida aquisição de freqüência e jitter reduzido. O filtro de loop adaptativo atualiza sua saída sempre que um valor PFD for recebido, amplia a largura de banda de loop PFL se um erro de fase grande for detectado, e estreita a largura de banda de loop se um erro de fase médio pequeno for detectado. O iDAC que pode ser implementado com ambas as fontes de corrente, guiada e de extremidade única, converte a saída de filtro de loop em corrente analógica. O ICO provê um sinal de oscilador tendo uma fase determinada pela saída iDAC. O divisor divide o sinal de oscilador por um fator de N e provê o sinal de realimentação.
BRPI0409107-8A 2003-04-09 2004-04-08 loop travado por fase digital BRPI0409107A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US46188903P 2003-04-09 2003-04-09
US10/644,490 US7042972B2 (en) 2003-04-09 2003-08-19 Compact, low-power low-jitter digital phase-locked loop
PCT/US2004/010866 WO2004093322A2 (en) 2003-04-09 2004-04-08 Digital phase-locked loop

Publications (1)

Publication Number Publication Date
BRPI0409107A true BRPI0409107A (pt) 2006-05-02

Family

ID=33135220

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0409107-8A BRPI0409107A (pt) 2003-04-09 2004-04-08 loop travado por fase digital

Country Status (6)

Country Link
US (1) US7042972B2 (pt)
KR (5) KR101040914B1 (pt)
BR (1) BRPI0409107A (pt)
IL (1) IL171309A (pt)
TW (1) TWI339507B (pt)
WO (1) WO2004093322A2 (pt)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005099103A1 (ja) * 2004-04-05 2005-10-20 Matsushita Electric Industrial Co., Ltd. 無線通信装置および無線通信方法
KR20070110829A (ko) * 2004-10-15 2007-11-20 프록심 와이어리스 코포레이션 리로드 검출을 위한 극성 반전 시스템 및 방법
US20060133559A1 (en) * 2004-12-22 2006-06-22 Glass Kevin W Programmable fractional N phase locked loop architecture and method
US20060285618A1 (en) * 2005-06-21 2006-12-21 Ehud Shoor Adaptive phase recovery
US7502602B2 (en) * 2005-07-19 2009-03-10 Intel Corporation Method and apparatus to compensate loop error of phase locked loop
KR100738734B1 (ko) * 2005-09-27 2007-07-12 인텔 코포레이션 클록 생성기를 포함하는 칩 및 마이크로 프로세서 시스템
US20070168085A1 (en) * 2005-11-18 2007-07-19 Guilford John H Systems and method for adaptively adjusting a control loop
US7933322B2 (en) * 2005-12-08 2011-04-26 Electronics And Telecommunications Research Institute Timing lock detection apparatus and method for digital broadcasting receiver
BRPI0708235A2 (pt) * 2006-02-24 2011-05-17 Nihon Dempa Kogyo Co circuito de pll
US7580498B2 (en) * 2006-05-18 2009-08-25 Via Technologies, Inc. Closed loop control system and method of dynamically changing the loop bandwidth
US7391271B2 (en) * 2006-06-22 2008-06-24 International Business Machines Corporation Adjustment of PLL bandwidth for jitter control using feedback circuitry
US7916824B2 (en) 2006-08-18 2011-03-29 Texas Instruments Incorporated Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique
US20080111633A1 (en) * 2006-11-09 2008-05-15 International Business Machines Corporation Systems and Arrangements for Controlling Phase Locked Loop
US7574327B2 (en) * 2006-12-12 2009-08-11 Sc Solutions All-digital cantilever controller
KR100833591B1 (ko) * 2006-12-27 2008-05-30 주식회사 하이닉스반도체 위상 동기 장치 및 위상 동기 신호 생성 방법
JP4264585B2 (ja) * 2007-04-27 2009-05-20 ソニー株式会社 同期回路およびその制御方法
WO2009034917A1 (ja) * 2007-09-12 2009-03-19 Nec Corporation ジッタ抑圧回路及びジッタ抑圧方法
US7940879B2 (en) * 2007-10-12 2011-05-10 Aptina Imaging Corporation Method and system of detecting and locking to multi-standard video streams
US8193866B2 (en) * 2007-10-16 2012-06-05 Mediatek Inc. All-digital phase-locked loop
US7737739B1 (en) * 2007-12-12 2010-06-15 Integrated Device Technology, Inc. Phase step clock generator
US8108453B2 (en) * 2007-12-17 2012-01-31 Applied Micro Circuits Corporation System and method for filter response switching
US7598803B2 (en) 2007-12-26 2009-10-06 National Kaohsiung University Of Applied Sciences Combined phase-locked loop and amplitude-locked loop module for switching FM signals
GB0800251D0 (en) * 2008-01-08 2008-02-13 Zarlink Semiconductor Inc Phase locked loop with adaptive filter for dco synchronization
US7893775B2 (en) * 2008-03-28 2011-02-22 Agilent Technologies, Inc. Frequency diverse discrete-time phase-lock device and apparatus
TWI360950B (en) 2008-10-09 2012-03-21 Univ Nat Chiao Tung Digital loop filter for all-digital phase-locked l
US8509371B2 (en) * 2009-09-29 2013-08-13 Analog Devices, Inc. Continuous-rate clock recovery circuit
US8324565B2 (en) * 2009-12-17 2012-12-04 Agilent Technologies, Inc. Ion funnel for mass spectrometry
US9344095B2 (en) * 2010-01-31 2016-05-17 Intel Mobile Communications GmbH Temperature compensation for an oscillator crystal
JP5537192B2 (ja) * 2010-03-04 2014-07-02 スパンション エルエルシー 受信装置及びゲイン設定方法
US8164499B1 (en) 2010-06-11 2012-04-24 Lattice Semiconductor Corporation Shared-array multiple-output digital-to-analog converter
CN102347761B (zh) * 2010-07-27 2014-02-19 中兴通讯股份有限公司南京分公司 一种动态延迟器及采用该延迟器的鉴频鉴相器和锁相环
US9344100B2 (en) 2010-10-05 2016-05-17 Qualcomm Incorporated Reconfigurable local oscillator for optimal noise performance in a multi-standard transceiver
KR101750414B1 (ko) * 2011-01-13 2017-06-23 삼성전자주식회사 디지털 위상 주파수 검출기, 이를 포함하는 디지털 위상 고정 루프 및 디지털 위상 주파수 검출 방법
TWI484759B (zh) * 2011-06-24 2015-05-11 Faraday Tech Corp 頻率鎖定方法、頻率鎖定電路、振盪器增益預測方法以及振盪器增益預測電路
US8461890B1 (en) * 2011-07-20 2013-06-11 United Microelectronics Corp. Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop
EP2632053B1 (en) * 2012-02-21 2014-08-27 ST-Ericsson SA PLL frequency selection
JP5915379B2 (ja) * 2012-05-25 2016-05-11 富士通株式会社 伝送装置および伝送方法
US8890592B2 (en) * 2012-10-13 2014-11-18 Infineon Technologies Ag Multi-output phase detector
US20140241335A1 (en) * 2013-02-28 2014-08-28 Qualcomm Incorporated Phase-locked loop using dual loop mode to achieve fast resettling
US9077351B2 (en) * 2013-03-13 2015-07-07 Samsung Electronics Co., Ltd. All-digital phase-locked loop for adaptively controlling closed-loop bandwidth, method of operating the same, and devices including the same
US20140354262A1 (en) * 2013-06-03 2014-12-04 Qualcomm Incorporated Lock detector for digital phase-locked loop
KR102090185B1 (ko) 2013-10-18 2020-03-17 현대모비스 주식회사 위상 잡음 최적화 장치 및 방법
KR101610625B1 (ko) * 2015-03-24 2016-04-08 고려대학교 산학협력단 물리적 복제 방지 기능을 이용한 기기 인증 시스템 및 방법
US9819481B2 (en) 2015-08-20 2017-11-14 Macnica Americas, Inc Clock recovery method and apparatus
US9893916B2 (en) * 2016-07-01 2018-02-13 Texas Instruments Incorporated Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop
US10749535B2 (en) 2017-06-28 2020-08-18 Analog Devices, Inc. Apparatus and methods for distributed timing using digital time stamps from a time-to-digital converter
US11038511B2 (en) 2017-06-28 2021-06-15 Analog Devices International Unlimited Company Apparatus and methods for system clock compensation
US10996634B2 (en) 2018-01-05 2021-05-04 Samsung Electronics Co., Ltd. System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)
US11018842B1 (en) * 2018-07-31 2021-05-25 Seagate Technology Llc Dynamic timing recovery bandwidth modulation for phase offset mitigation
US11424748B1 (en) 2021-08-10 2022-08-23 Nxp B.V. Modified PID loop filter to suppress high frequency noise in digital phase locked loop
US11646743B1 (en) 2022-03-09 2023-05-09 Nxp Usa, Inc. Digital phase-locked loop
CN121263958A (zh) * 2023-07-18 2026-01-02 德州仪器公司 带有具有干扰响应的锁相环的电路
WO2025149155A1 (en) * 2024-01-11 2025-07-17 Telefonaktiebolaget Lm Ericsson (Publ) Digital phase locked loop system and method for integral gain calibration

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703539A (en) * 1993-12-17 1997-12-30 Motorola, Inc. Apparatus and method for controlling the loop bandwidth of a phase locked loop
JPH07231688A (ja) * 1994-02-10 1995-08-29 Toshiba Corp Ｐｌｌシステム
JP3679503B2 (ja) * 1996-06-11 2005-08-03 松下電器産業株式会社 周波数シンセサイザ
US6236275B1 (en) * 1997-10-24 2001-05-22 Ericsson Inc. Digital frequency synthesis by sequential fraction approximations
US6054903A (en) * 1997-11-13 2000-04-25 Lsi Logic Corporation Dual-loop PLL with adaptive time constant reduction on first loop
US6606364B1 (en) * 1999-03-04 2003-08-12 Harris Corporation Multiple data rate bit synchronizer having phase/frequency detector gain constant proportional to PLL clock divider ratio
US6414555B2 (en) 2000-03-02 2002-07-02 Texas Instruments Incorporated Frequency synthesizer

Also Published As

Publication number Publication date
KR20050122250A (ko) 2005-12-28
IL171309A (en) 2010-05-31
KR101040915B1 (ko) 2011-06-16
TWI339507B (en) 2011-03-21
KR20110017022A (ko) 2011-02-18
KR101040913B1 (ko) 2011-06-16
KR101040916B1 (ko) 2011-06-16
KR101080658B1 (ko) 2011-11-08
KR101040914B1 (ko) 2011-06-16
TW200501587A (en) 2005-01-01
WO2004093322A2 (en) 2004-10-28
KR20110017021A (ko) 2011-02-18
WO2004093322A3 (en) 2005-03-24
KR20110018466A (ko) 2011-02-23
US20040202271A1 (en) 2004-10-14
US7042972B2 (en) 2006-05-09
KR20110018467A (ko) 2011-02-23

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 11A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2307 DE 24/03/2015.