BRPI0501160A - Aparelho processador de vetores - Google Patents

Aparelho processador de vetores

Info

Publication number
BRPI0501160A
BRPI0501160A BR0501160-4A BRPI0501160A BRPI0501160A BR PI0501160 A BRPI0501160 A BR PI0501160A BR PI0501160 A BRPI0501160 A BR PI0501160A BR PI0501160 A BRPI0501160 A BR PI0501160A
Authority
BR
Brazil
Prior art keywords
instruction
instructions
group
specific
main memory
Prior art date
Application number
BR0501160-4A
Other languages
English (en)
Inventor
Yasumasa Saida
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of BRPI0501160A publication Critical patent/BRPI0501160A/pt

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D1/00—Working stone or stone-like materials, e.g. brick, concrete or glass, not provided for elsewhere; Machines, devices, tools therefor
    • B28D1/14—Working stone or stone-like materials, e.g. brick, concrete or glass, not provided for elsewhere; Machines, devices, tools therefor by boring or drilling
    • B28D1/146—Tools therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23B—TURNING; BORING
    • B23B47/00—Constructional features of components specially designed for boring or drilling machines; Accessories therefor
    • B23B47/34—Arrangements for removing chips out of the holes made; Chip- breaking arrangements attached to the tool
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Mechanical Engineering (AREA)
  • Mining & Mineral Resources (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)

Abstract

"APARELHO PROCESSADOR DE VETORES". Um aparelho processador de vetores inclui uma memória principal (200), uma seção de emissão de instrução (3), um circuito de controle de ultrapassagem (1) e uma seção de execução de instrução (3). A seção de emissão de instrução emite seq³encialmente instruções. Uma primeira instrução das instruções é emitida, e então uma segunda instrução da mesma é emitida, uma quarta instrução da mesma é emitida antes de uma terceira instrução da mesma a qual é emitida após a segunda instrução. O circuito de controle de ultrapassagem emite as instruções recebidas da seção de emissão de instrução para a seção de execução de instrução em uma ordem determinada baseado em se cada uma de a primeira e a segunda instruções com duas das instruções recebidas pertence a um primeiro grupo específico de instruções, se cada uma de a primeira e a segunda instruções pertence a um segundo grupo específico de instruções no primeiro grupo específico de instruções, se a quarta instrução como uma das instruções recebidas é um quarto grupo específico de instruções, se uma terceira instrução como uma das instruções recebidas pertence a um terceiro grupo específico de instruções, e se uma área de endereço da memória principal relacionada com a terceira instrução e uma área de endereço da memória principal relacionada com cada uma de a primeira e a segunda instruções não se sobrepõem ao todo. A seção de execução de instrução executa as instruções recebidas do circuito de controle de ultrapassagem em uma ordem de recepção e para acessar a memória principal em resposta a cada uma de a primeira à terceira instruções das instruções.
BR0501160-4A 2004-02-23 2005-02-23 Aparelho processador de vetores BRPI0501160A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004047066A JP3988144B2 (ja) 2004-02-23 2004-02-23 ベクトル処理装置、及び、追い越し制御回路

Publications (1)

Publication Number Publication Date
BRPI0501160A true BRPI0501160A (pt) 2005-10-18

Family

ID=34747424

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0501160-4A BRPI0501160A (pt) 2004-02-23 2005-02-23 Aparelho processador de vetores

Country Status (7)

Country Link
US (1) US7526629B2 (pt)
EP (1) EP1569091A3 (pt)
JP (1) JP3988144B2 (pt)
KR (1) KR100636759B1 (pt)
AU (1) AU2005200812A1 (pt)
BR (1) BRPI0501160A (pt)
CA (1) CA2497807A1 (pt)

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US8495602B2 (en) * 2007-09-28 2013-07-23 Qualcomm Incorporated Shader compile system and method
JP5573134B2 (ja) * 2009-12-04 2014-08-20 日本電気株式会社 ベクトル型計算機及びベクトル型計算機の命令制御方法
JP5585304B2 (ja) * 2010-08-25 2014-09-10 日本電気株式会社 データ処理装置、メモリアクセス制御方法及びメモリアクセス制御プログラム
JP5630281B2 (ja) * 2011-01-19 2014-11-26 日本電気株式会社 ベクトル命令制御回路及びリストベクトルの追い越し制御方法
JP5732953B2 (ja) * 2011-03-24 2015-06-10 日本電気株式会社 ベクトル処理装置、ベクトル処理方法、及び、プログラム
US8521705B2 (en) * 2011-07-11 2013-08-27 Dell Products L.P. Accelerated deduplication
US9021233B2 (en) * 2011-09-28 2015-04-28 Arm Limited Interleaving data accesses issued in response to vector access instructions
WO2013095613A2 (en) 2011-12-23 2013-06-27 Intel Corporation Apparatus and method of mask permute instructions
US9946540B2 (en) 2011-12-23 2018-04-17 Intel Corporation Apparatus and method of improved permute instructions with multiple granularities
US9619236B2 (en) 2011-12-23 2017-04-11 Intel Corporation Apparatus and method of improved insert instructions
US9588764B2 (en) 2011-12-23 2017-03-07 Intel Corporation Apparatus and method of improved extract instructions
CN104011616B (zh) 2011-12-23 2017-08-29 英特尔公司 改进置换指令的装置和方法
US20130173886A1 (en) * 2012-01-04 2013-07-04 Qualcomm Incorporated Processor with Hazard Tracking Employing Register Range Compares
CN104303142B (zh) 2012-06-02 2019-03-08 英特尔公司 使用索引阵列和有限状态机的分散
US8972697B2 (en) * 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US9098265B2 (en) * 2012-07-11 2015-08-04 Arm Limited Controlling an order for processing data elements during vector processing
JP6256088B2 (ja) * 2014-02-20 2018-01-10 日本電気株式会社 ベクトルプロセッサ、情報処理装置および追い越し制御方法
US9891914B2 (en) * 2015-04-10 2018-02-13 Intel Corporation Method and apparatus for performing an efficient scatter
CN108595371B (zh) * 2016-01-20 2019-11-19 北京中科寒武纪科技有限公司 用于向量运算的数据读取、写入及读写调度器及保留站
GB2554096B (en) * 2016-09-20 2019-03-20 Advanced Risc Mach Ltd Handling of inter-element address hazards for vector instructions
US10474461B2 (en) 2016-09-22 2019-11-12 Qualcomm Incorporated Instruction-based synchronization of operations including at least one SIMD scatter operation
US11093438B2 (en) * 2019-01-07 2021-08-17 International Business Machines Corporation Pipelining multi-directional reduction

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JPH0810451B2 (ja) 1989-03-28 1996-01-31 日本電気株式会社 情報処理装置
JPH04369773A (ja) 1991-06-19 1992-12-22 Nec Corp 情報処理装置
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Also Published As

Publication number Publication date
KR100636759B1 (ko) 2006-10-20
US20050188178A1 (en) 2005-08-25
AU2005200812A1 (en) 2005-09-08
CA2497807A1 (en) 2005-08-23
JP2005235135A (ja) 2005-09-02
KR20060043130A (ko) 2006-05-15
US7526629B2 (en) 2009-04-28
EP1569091A2 (en) 2005-08-31
JP3988144B2 (ja) 2007-10-10
EP1569091A3 (en) 2008-01-16

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Legal Events

Date Code Title Description
B03A Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 5A E 6A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2086 DE 28/12/2010.