BRPI0509082A - sistema de memória em cache e controlador de cache para processador de sinais digitais embutido - Google Patents

sistema de memória em cache e controlador de cache para processador de sinais digitais embutido

Info

Publication number
BRPI0509082A
BRPI0509082A BRPI0509082-2A BRPI0509082A BRPI0509082A BR PI0509082 A BRPI0509082 A BR PI0509082A BR PI0509082 A BRPI0509082 A BR PI0509082A BR PI0509082 A BRPI0509082 A BR PI0509082A
Authority
BR
Brazil
Prior art keywords
memory
cache
chip
built
digital signal
Prior art date
Application number
BRPI0509082-2A
Other languages
English (en)
Inventor
Gilbert Christopher Sih
Charles E Sakamaki
De D Hsu
Jian Wei
Richard Higgins
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0509082A publication Critical patent/BRPI0509082A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/253—Centralized memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)

Abstract

SISTEMA DE MEMóRIA EM CACHE E CONTROLADOR DE CACHE PARA PROCESSADOR DE SINAIS DIGITAIS EMBUTIDO é descrito, um sistema de memória em cache que pode processar dados de entrada de taxa alta e asseguar que um DSP embutido satisfaça limitações em tempo real. O sistema de memória em cache inclui uma memória cache localizada próximo de um núcleo de processador, uma memória no chip ao nível de memória mais alto seguinte e uma memória principal externa ao nível de memória mais alto. Um controlador de cache lida com a paginação de intruções e dados entre a memória cache e a memória no chip para perdas de cache. Um controlador de troca direta de memória (DME) lida com a paginação controlada pelo usuário entre a memória no chip e a memória externa. O usuário/propramador pode providenciar para que as intruções e dados de que necessita o núcleo de processador estejam presentes na memória no chip bem antes do momento em que o núcleo de processador necessita realmente delas.
BRPI0509082-2A 2004-03-24 2005-03-11 sistema de memória em cache e controlador de cache para processador de sinais digitais embutido BRPI0509082A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/807,648 US7769950B2 (en) 2004-03-24 2004-03-24 Cached memory system and cache controller for embedded digital signal processor
PCT/US2005/008373 WO2005101213A2 (en) 2004-03-24 2005-03-11 Cached memory system and cache controller for embedded digital signal processor

Publications (1)

Publication Number Publication Date
BRPI0509082A true BRPI0509082A (pt) 2007-08-21

Family

ID=34964028

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0509082-2A BRPI0509082A (pt) 2004-03-24 2005-03-11 sistema de memória em cache e controlador de cache para processador de sinais digitais embutido

Country Status (7)

Country Link
US (2) US7769950B2 (pt)
KR (3) KR100974024B1 (pt)
BR (1) BRPI0509082A (pt)
IL (1) IL178258A0 (pt)
SG (1) SG151304A1 (pt)
TW (1) TW200608203A (pt)
WO (1) WO2005101213A2 (pt)

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Also Published As

Publication number Publication date
WO2005101213A3 (en) 2006-01-26
TW200608203A (en) 2006-03-01
SG151304A1 (en) 2009-04-30
WO2005101213A2 (en) 2005-10-27
US20100235578A1 (en) 2010-09-16
KR20060133054A (ko) 2006-12-22
IL178258A0 (en) 2006-12-31
US7769950B2 (en) 2010-08-03
KR100974024B1 (ko) 2010-08-05
US20050216666A1 (en) 2005-09-29
US8316185B2 (en) 2012-11-20
KR100940961B1 (ko) 2010-02-05
KR20080016753A (ko) 2008-02-21
KR20080091379A (ko) 2008-10-10

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2158 DE 15/05/2012.