BRPI0608200A2 - leitura de registrador para memória volátil - Google Patents

leitura de registrador para memória volátil

Info

Publication number
BRPI0608200A2
BRPI0608200A2 BRPI0608200-9A BRPI0608200A BRPI0608200A2 BR PI0608200 A2 BRPI0608200 A2 BR PI0608200A2 BR PI0608200 A BRPI0608200 A BR PI0608200A BR PI0608200 A2 BRPI0608200 A2 BR PI0608200A2
Authority
BR
Brazil
Prior art keywords
read command
register read
data
read
stored
Prior art date
Application number
BRPI0608200-9A
Other languages
English (en)
Inventor
Robert Michael Walker
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0608200A2 publication Critical patent/BRPI0608200A2/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

LEITURA DE REGISTRADOR PARA MEMóRIA VOLáTIL. Dados não armazenados no arranjo DRAM (104) de um módulo SDRAM (100) são udos do módulo SDRAM em uma transferência de dados síncrona. A transferência de dados, referida como operação/comando de leitura de registrador, assemelha-se a um comando/operação de leitura direcionada a dados armazenados no arranjo DRAM em temporização e operação. O comando de leitura de registrador se distingue por uma codificação exclusiva dos sinais de controle de SDRAM e bits de endereço de banco. Em uma modalidade, o comando de leitura de registrador compreende os mesmos estados dos sinais de controle de um comando MRS ou EMRS, com o endereço de banco ajustado a um valor único, tal como 2b10. O comando de leitura de registrador pode ler apenas um único dado, ou pode utilizar o barramento de endereço para endereçar uma pluralidade de dados não armazenados no arranjo DRAM. A operação de leitura de registrador pode ser uma leitura em rajada, e o comprimento de rajada pode ser definido de diversas maneiras.
BRPI0608200-9A 2005-02-14 2006-02-03 leitura de registrador para memória volátil BRPI0608200A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US65302005P 2005-02-14 2005-02-14
US11/128,829 US7230876B2 (en) 2005-02-14 2005-05-13 Register read for volatile memory
PCT/US2006/006995 WO2006089313A2 (en) 2005-02-14 2006-02-03 Register read for volatile memory

Publications (1)

Publication Number Publication Date
BRPI0608200A2 true BRPI0608200A2 (pt) 2009-12-01

Family

ID=36587043

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0608200-9A BRPI0608200A2 (pt) 2005-02-14 2006-02-03 leitura de registrador para memória volátil

Country Status (11)

Country Link
US (2) US7230876B2 (pt)
EP (2) EP1849161B1 (pt)
JP (3) JP5490361B2 (pt)
KR (1) KR100884448B1 (pt)
CN (1) CN101156211B (pt)
AT (1) ATE475180T1 (pt)
BR (1) BRPI0608200A2 (pt)
DE (1) DE602006015613D1 (pt)
ES (1) ES2393715T3 (pt)
IL (1) IL185249A (pt)
WO (1) WO2006089313A2 (pt)

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US7120084B2 (en) * 2004-06-14 2006-10-10 Marvell International Ltd. Integrated memory controller
US8122187B2 (en) * 2004-07-02 2012-02-21 Qualcomm Incorporated Refreshing dynamic volatile memory
KR20060084071A (ko) * 2005-01-17 2006-07-24 삼성전자주식회사 반도체 메모리에서의 리프레쉬 제어회로 및 그에 따른제어방법
US7640392B2 (en) 2005-06-23 2009-12-29 Qualcomm Incorporated Non-DRAM indicator and method of accessing data not stored in DRAM array
US7620783B2 (en) * 2005-02-14 2009-11-17 Qualcomm Incorporated Method and apparatus for obtaining memory status information cross-reference to related applications
US7230876B2 (en) 2005-02-14 2007-06-12 Qualcomm Incorporated Register read for volatile memory
US7610455B2 (en) * 2005-05-11 2009-10-27 Infineon Technologies Ag Technique to read special mode register
US9262326B2 (en) * 2006-08-14 2016-02-16 Qualcomm Incorporated Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
US20080056051A1 (en) * 2006-08-31 2008-03-06 Peter Mayer Memory with memory banks and mode registers and method of operating a memory
US7593279B2 (en) * 2006-10-11 2009-09-22 Qualcomm Incorporated Concurrent status register read
KR100919815B1 (ko) * 2008-08-04 2009-10-01 주식회사 하이닉스반도체 반도체 메모리 장치
KR101529675B1 (ko) * 2008-12-26 2015-06-29 삼성전자주식회사 멀티 칩 패키지 메모리 장치
JP5441216B2 (ja) * 2010-02-24 2014-03-12 ルネサスエレクトロニクス株式会社 半導体装置及びデータ処理システム
DE112011106086B4 (de) * 2011-12-22 2024-11-07 Intel Corporation Zugreifen auf daten, die in einem befehls-/adressregister-gerät gespeichert sind
US8787105B2 (en) * 2012-05-10 2014-07-22 Nanya Technology Corporation Dynamic random access memory with multiple thermal sensors disposed therein and control method thereof
US10050610B2 (en) 2015-03-10 2018-08-14 Qualcomm Incorporated Clock distribution schemes with wide operating voltage ranges
US10223311B2 (en) 2015-03-30 2019-03-05 Samsung Electronics Co., Ltd. Semiconductor memory device for sharing inter-memory command and information, memory system including the same and method of operating the memory system
KR102372888B1 (ko) * 2015-06-15 2022-03-10 삼성전자주식회사 저장 장치의 온도별 데이터 관리 방법
US10395722B2 (en) * 2017-09-29 2019-08-27 Intel Corporation Reading from a mode register having different read and write timing
US10649925B2 (en) 2018-05-16 2020-05-12 Microsoft Technology Licensing, Llc Indirect data return from memory controller logic
US10489316B1 (en) 2018-06-04 2019-11-26 Micron Technology, Inc. Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
US11189327B2 (en) * 2019-08-21 2021-11-30 Micron Technology, Inc. Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same
CN115145466B (zh) * 2021-03-29 2025-02-25 长鑫存储技术有限公司 数据传输电路、方法及存储装置
CN115132240B (zh) * 2021-03-29 2024-06-28 长鑫存储技术有限公司 数据传输电路、方法及存储装置
CN116417034A (zh) * 2021-12-31 2023-07-11 瑞昱半导体股份有限公司 用于同步动态随机存取存储器之设置模块及其设置方法
KR102428901B1 (ko) 2022-04-15 2022-08-04 삼성전자주식회사 명령어 로그 레지스터를 포함하는 반도체 메모리 장치 및 그것의 명령어 로그 출력 방법

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US8122187B2 (en) * 2004-07-02 2012-02-21 Qualcomm Incorporated Refreshing dynamic volatile memory
US7230876B2 (en) 2005-02-14 2007-06-12 Qualcomm Incorporated Register read for volatile memory

Also Published As

Publication number Publication date
EP2234114B1 (en) 2012-10-03
EP1849161A2 (en) 2007-10-31
KR20070103060A (ko) 2007-10-22
US7230876B2 (en) 2007-06-12
DE602006015613D1 (de) 2010-09-02
IL185249A0 (en) 2008-02-09
ATE475180T1 (de) 2010-08-15
ES2393715T3 (es) 2012-12-27
JP2014211939A (ja) 2014-11-13
US7251192B2 (en) 2007-07-31
IL185249A (en) 2012-07-31
JP2012119055A (ja) 2012-06-21
CN101156211A (zh) 2008-04-02
KR100884448B1 (ko) 2009-02-19
CN101156211B (zh) 2013-08-14
EP2234114A1 (en) 2010-09-29
JP2008530721A (ja) 2008-08-07
WO2006089313A3 (en) 2007-01-18
JP5490361B2 (ja) 2014-05-14
US20060181957A1 (en) 2006-08-17
US20070115744A1 (en) 2007-05-24
WO2006089313A2 (en) 2006-08-24
EP1849161B1 (en) 2010-07-21

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 6A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2161 DE 05/06/2012.