BRPI0722059A2 - Método para incorporar matriz de silício existente dentro de pilha integrada de 3d - Google Patents

Método para incorporar matriz de silício existente dentro de pilha integrada de 3d

Info

Publication number
BRPI0722059A2
BRPI0722059A2 BRPI0722059-6A2A BRPI0722059A BRPI0722059A2 BR PI0722059 A2 BRPI0722059 A2 BR PI0722059A2 BR PI0722059 A BRPI0722059 A BR PI0722059A BR PI0722059 A2 BRPI0722059 A2 BR PI0722059A2
Authority
BR
Brazil
Prior art keywords
matrix
integrated battery
silence
entering existing
entering
Prior art date
Application number
BRPI0722059-6A2A
Other languages
English (en)
Inventor
Paul Reed Riewerts
Bryan Black
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=39541641&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=BRPI0722059(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Intel Corp filed Critical Intel Corp
Publication of BRPI0722059A2 publication Critical patent/BRPI0722059A2/pt
Publication of BRPI0722059B1 publication Critical patent/BRPI0722059B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
BRPI0722059-6A 2006-12-20 2007-12-06 aparelho, método e sistema para incorporar matriz de silício existente dentro de pilha integrada de 3d BRPI0722059B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/613,774 2006-12-20
US11/613,774 US8110899B2 (en) 2006-12-20 2006-12-20 Method for incorporating existing silicon die into 3D integrated stack
PCT/US2007/086674 WO2008079625A1 (en) 2006-12-20 2007-12-06 Method for incorporating existing silicon die into 3d integrated stack

Publications (2)

Publication Number Publication Date
BRPI0722059A2 true BRPI0722059A2 (pt) 2014-04-01
BRPI0722059B1 BRPI0722059B1 (pt) 2018-10-09

Family

ID=39541641

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0722059-6A BRPI0722059B1 (pt) 2006-12-20 2007-12-06 aparelho, método e sistema para incorporar matriz de silício existente dentro de pilha integrada de 3d

Country Status (6)

Country Link
US (1) US8110899B2 (pt)
CN (2) CN101563773B (pt)
BR (1) BRPI0722059B1 (pt)
DE (3) DE112007003816B4 (pt)
RU (1) RU2419179C2 (pt)
WO (1) WO2008079625A1 (pt)

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WO2008079625A1 (en) 2008-07-03
CN101563773B (zh) 2012-05-30
CN102610596B (zh) 2015-09-16
DE112007003111T5 (de) 2009-11-05
CN101563773A (zh) 2009-10-21
CN102610596A (zh) 2012-07-25
RU2419179C2 (ru) 2011-05-20
BRPI0722059B1 (pt) 2018-10-09
US20080150088A1 (en) 2008-06-26
DE112007003816B4 (de) 2025-10-09
DE112007003111B4 (de) 2020-06-18
US8110899B2 (en) 2012-02-07
RU2009127834A (ru) 2011-01-27
DE112007003820B4 (de) 2026-03-12

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