BRPI0913033A2 - projeto de pad para mram-stt - Google Patents
projeto de pad para mram-sttInfo
- Publication number
- BRPI0913033A2 BRPI0913033A2 BRPI0913033A BRPI0913033A BRPI0913033A2 BR PI0913033 A2 BRPI0913033 A2 BR PI0913033A2 BR PI0913033 A BRPI0913033 A BR PI0913033A BR PI0913033 A BRPI0913033 A BR PI0913033A BR PI0913033 A2 BRPI0913033 A2 BR PI0913033A2
- Authority
- BR
- Brazil
- Prior art keywords
- stt
- mram
- pad design
- pad
- design
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/495—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/125,113 US20090290406A1 (en) | 2008-05-22 | 2008-05-22 | Low loading pad design for STT MRAM or other short pulse signal transmission |
| PCT/US2009/043346 WO2009142931A1 (en) | 2008-05-22 | 2009-05-08 | Pad design for stt-mram |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BRPI0913033A2 true BRPI0913033A2 (pt) | 2018-02-06 |
Family
ID=41055186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BRPI0913033A BRPI0913033A2 (pt) | 2008-05-22 | 2009-05-08 | projeto de pad para mram-stt |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20090290406A1 (pt) |
| JP (1) | JP2011523781A (pt) |
| KR (1) | KR20110005849A (pt) |
| CN (1) | CN102027595A (pt) |
| BR (1) | BRPI0913033A2 (pt) |
| CA (1) | CA2723830A1 (pt) |
| MX (1) | MX2010012671A (pt) |
| TW (1) | TW201004005A (pt) |
| WO (1) | WO2009142931A1 (pt) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8094486B2 (en) * | 2008-05-22 | 2012-01-10 | Qualcomm Incorporated | Pad design with buffers for STT-MRAM or other short pulse signal transmission |
| US12041787B2 (en) | 2019-05-02 | 2024-07-16 | Sandisk Technologies Llc | Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning |
| US12004356B2 (en) | 2019-05-02 | 2024-06-04 | Sandisk Technologies Llc | Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning |
| US12004357B2 (en) | 2019-05-02 | 2024-06-04 | Sandisk Technologies Llc | Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning |
| US12402324B2 (en) | 2019-05-02 | 2025-08-26 | SanDisk Technologies, Inc. | Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning |
| US11152425B2 (en) | 2019-10-29 | 2021-10-19 | Western Digital Technologies, Inc. | Cross-point spin-transfer torque magnetoresistive memory array and method of making the same |
| CN112837723A (zh) * | 2019-11-22 | 2021-05-25 | 上海磁宇信息科技有限公司 | 错层式金属位线走线的磁性随机存储器存储阵列 |
| US12543508B2 (en) | 2022-03-14 | 2026-02-03 | SanDisk Technologies, Inc. | Cross-point magnetoresistive memory array containing selector rails and method of making the same |
| US12414307B2 (en) | 2022-03-14 | 2025-09-09 | SanDisk Technologies, Inc. | Cross-point magnetoresistive memory array including self-aligned dielectric spacers and method of making thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6927073B2 (en) * | 2002-05-16 | 2005-08-09 | Nova Research, Inc. | Methods of fabricating magnetoresistive memory devices |
| US6909196B2 (en) * | 2002-06-21 | 2005-06-21 | Micron Technology, Inc. | Method and structures for reduced parasitic capacitance in integrated circuit metallizations |
| JP2004040006A (ja) * | 2002-07-08 | 2004-02-05 | Sony Corp | 磁気メモリ装置およびその製造方法 |
| US6933547B2 (en) * | 2003-06-11 | 2005-08-23 | Broadcom Corporation | Memory cell for modification of default register values in an integrated circuit chip |
-
2008
- 2008-05-22 US US12/125,113 patent/US20090290406A1/en not_active Abandoned
-
2009
- 2009-05-08 JP JP2011510566A patent/JP2011523781A/ja active Pending
- 2009-05-08 KR KR1020107025317A patent/KR20110005849A/ko not_active Ceased
- 2009-05-08 MX MX2010012671A patent/MX2010012671A/es not_active Application Discontinuation
- 2009-05-08 CA CA2723830A patent/CA2723830A1/en not_active Abandoned
- 2009-05-08 CN CN2009801176959A patent/CN102027595A/zh active Pending
- 2009-05-08 BR BRPI0913033A patent/BRPI0913033A2/pt not_active IP Right Cessation
- 2009-05-08 WO PCT/US2009/043346 patent/WO2009142931A1/en not_active Ceased
- 2009-05-21 TW TW098116948A patent/TW201004005A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR20110005849A (ko) | 2011-01-19 |
| CA2723830A1 (en) | 2009-11-26 |
| TW201004005A (en) | 2010-01-16 |
| JP2011523781A (ja) | 2011-08-18 |
| MX2010012671A (es) | 2010-12-21 |
| WO2009142931A1 (en) | 2009-11-26 |
| CN102027595A (zh) | 2011-04-20 |
| US20090290406A1 (en) | 2009-11-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B08F | Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette] | ||
| B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |