BRPI1001929A2 - Execução atômica remota de manipulação adaptativa - Google Patents

Execução atômica remota de manipulação adaptativa

Info

Publication number
BRPI1001929A2
BRPI1001929A2 BRPI1001929-4A2A BRPI1001929A BRPI1001929A2 BR PI1001929 A2 BRPI1001929 A2 BR PI1001929A2 BR PI1001929 A BRPI1001929 A BR PI1001929A BR PI1001929 A2 BRPI1001929 A2 BR PI1001929A2
Authority
BR
Brazil
Prior art keywords
instruction
implementation
remote atomic
adaptive
manipulation
Prior art date
Application number
BRPI1001929-4A2A
Other languages
English (en)
Inventor
Joshua B Fryman
Toni Juan
John Mejia
Eric Sprangle
Ravi Rajwar
Edward T Grochowski
Andrew Thomas Forsyth
Ramacharan Sundarararman
Roger Espasa
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BRPI1001929A2 publication Critical patent/BRPI1001929A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Computer And Data Communications (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

EXECUÇÃO ATÔMICA REMOTA DE MANIPULAÇÃO ADAPTATIVA A presente invenção refere-se a uma concretização, um método que inclui o recebimento de uma instrução para decodíficação em um núcleo de processador e a manipulação dinâmica da instrução com um dos múltiplos comportamentos com base em se a contenção é prevista. Se nenhuma contenção for prevista, a instrução sera executada no núcleo, e se a contenção for prevista, dados associados com a instrução serão ordenados e enviados para um agente remoto selecionado para execução. Outras concretizações são descritas e reivindicadas.
BRPI1001929-4A2A 2009-06-26 2010-06-25 Execução atômica remota de manipulação adaptativa BRPI1001929A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/492,652 US8533436B2 (en) 2009-06-26 2009-06-26 Adaptively handling remote atomic execution based upon contention prediction

Publications (1)

Publication Number Publication Date
BRPI1001929A2 true BRPI1001929A2 (pt) 2014-02-18

Family

ID=43382048

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI1001929-4A2A BRPI1001929A2 (pt) 2009-06-26 2010-06-25 Execução atômica remota de manipulação adaptativa

Country Status (4)

Country Link
US (1) US8533436B2 (pt)
KR (1) KR101168544B1 (pt)
CN (1) CN101937331B (pt)
BR (1) BRPI1001929A2 (pt)

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US9122476B2 (en) 2010-12-07 2015-09-01 Advanced Micro Devices, Inc. Programmable atomic memory using hardware validation agent
US8788794B2 (en) * 2010-12-07 2014-07-22 Advanced Micro Devices, Inc. Programmable atomic memory using stored atomic procedures
US10007523B2 (en) * 2011-05-02 2018-06-26 International Business Machines Corporation Predicting cache misses using data access behavior and instruction address
US8832505B2 (en) 2012-06-29 2014-09-09 Intel Corporation Methods and apparatus to provide failure detection
US9792252B2 (en) 2013-05-31 2017-10-17 Microsoft Technology Licensing, Llc Incorporating a spatial array into one or more programmable processor cores
CN104216684B (zh) * 2013-06-04 2017-05-31 阿里巴巴集团控股有限公司 一种多核并行系统及其数据处理方法
GB2518613A (en) 2013-09-25 2015-04-01 Ibm Multiple core processing with high throughput atomic memory operations
US9471397B2 (en) 2014-10-03 2016-10-18 International Business Machines Corporation Global lock contention predictor
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10127153B1 (en) 2015-09-28 2018-11-13 Apple Inc. Cache dependency handling
US10901940B2 (en) 2016-04-02 2021-01-26 Intel Corporation Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
US20200401412A1 (en) * 2019-06-24 2020-12-24 Intel Corporation Hardware support for dual-memory atomic operations
US20200242042A1 (en) * 2020-03-26 2020-07-30 Jonas Svennebring System, Apparatus and Method for Performing a Remote Atomic Operation Via an Interface
US11119767B1 (en) 2020-06-19 2021-09-14 Apple Inc. Atomic operation predictor to predict if an atomic operation will successfully complete and a store queue to selectively forward data based on the predictor

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US5161227A (en) 1989-11-13 1992-11-03 International Business Machines Corporation Multilevel locking system and method
US6240414B1 (en) 1997-09-28 2001-05-29 Eisolutions, Inc. Method of resolving data conflicts in a shared data environment
US6032242A (en) 1997-10-15 2000-02-29 Industrial Technology Research Institute Methods and systems for generating alternate and zigzag address scans based on feedback addresses of alternate and zigzag access patterns
US6182210B1 (en) 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6651088B1 (en) 1999-07-20 2003-11-18 Hewlett-Packard Development Company, L.P. Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
US7243356B1 (en) 2000-05-09 2007-07-10 Sun Microsystems, Inc. Remote method invocation with secure messaging in a distributed computing environment
US6678772B2 (en) 2000-12-19 2004-01-13 International Businesss Machines Corporation Adaptive reader-writer lock
US6950945B2 (en) 2001-06-21 2005-09-27 International Business Machines Corporation Apparatus and method for intersystem lock optimization
US7159220B2 (en) 2001-09-28 2007-01-02 Intel Corporation Flexible acceleration of java thread synchronization on multiprocessor computers
US7120762B2 (en) 2001-10-19 2006-10-10 Wisconsin Alumni Research Foundation Concurrent execution of critical sections by eliding ownership of locks
US7529914B2 (en) 2004-06-30 2009-05-05 Intel Corporation Method and apparatus for speculative execution of uncontended lock instructions
US7516313B2 (en) 2004-12-29 2009-04-07 Intel Corporation Predicting contention in a processor
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Also Published As

Publication number Publication date
KR101168544B1 (ko) 2012-07-27
US8533436B2 (en) 2013-09-10
CN101937331B (zh) 2015-05-06
US20100332801A1 (en) 2010-12-30
CN101937331A (zh) 2011-01-05
KR20110000533A (ko) 2011-01-03

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Legal Events

Date Code Title Description
B03A Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]
B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]