CA1020284A - Etage tampon entre les unites de memoire et de calcul d'un ordinateur - Google Patents

Etage tampon entre les unites de memoire et de calcul d'un ordinateur

Info

Publication number
CA1020284A
CA1020284A CA221,327A CA221327A CA1020284A CA 1020284 A CA1020284 A CA 1020284A CA 221327 A CA221327 A CA 221327A CA 1020284 A CA1020284 A CA 1020284A
Authority
CA
Canada
Prior art keywords
memory
computer
buffer apparatus
calculator
portions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA221,327A
Other languages
English (en)
Inventor
Kurt Erben
Maurice L. Hutson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Control Data Corp filed Critical Control Data Corp
Priority to CA280,700A priority Critical patent/CA1023054A/fr
Application granted granted Critical
Publication of CA1020284A publication Critical patent/CA1020284A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
CA221,327A 1974-05-17 1975-03-05 Etage tampon entre les unites de memoire et de calcul d'un ordinateur Expired CA1020284A (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA280,700A CA1023054A (fr) 1974-05-17 1977-06-16 Systeme de traitement de donnees

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US470896A US3919534A (en) 1974-05-17 1974-05-17 Data processing system

Publications (1)

Publication Number Publication Date
CA1020284A true CA1020284A (fr) 1977-11-01

Family

ID=23869506

Family Applications (1)

Application Number Title Priority Date Filing Date
CA221,327A Expired CA1020284A (fr) 1974-05-17 1975-03-05 Etage tampon entre les unites de memoire et de calcul d'un ordinateur

Country Status (2)

Country Link
US (1) US3919534A (fr)
CA (1) CA1020284A (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5725069A (en) * 1980-07-21 1982-02-09 Hitachi Ltd Vector data processing equipment
US4371951A (en) * 1980-09-29 1983-02-01 Control Data Corporation Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units
JPS57209570A (en) * 1981-06-19 1982-12-22 Fujitsu Ltd Vector processing device
JPS5975365A (ja) * 1982-10-22 1984-04-28 Hitachi Ltd ベクトル処理装置
US4661900A (en) * 1983-04-25 1987-04-28 Cray Research, Inc. Flexible chaining in vector processor with selective use of vector registers as operand and result registers
JPS6015771A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd ベクトルプロセッサ
US5142638A (en) * 1989-02-07 1992-08-25 Cray Research, Inc. Apparatus for sharing memory in a multiprocessor system
EP0485522A4 (en) * 1990-05-30 1993-08-04 Daniel W. Hammerstrom Neural network using virtual-zero
US5369773A (en) * 1991-04-26 1994-11-29 Adaptive Solutions, Inc. Neural network using virtual-zero
US5642306A (en) * 1994-07-27 1997-06-24 Intel Corporation Method and apparatus for a single instruction multiple data early-out zero-skip multiplier
US7788285B2 (en) * 2004-05-14 2010-08-31 Oracle International Corporation Finer grain dependency tracking for database objects
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations
US10460704B2 (en) 2016-04-01 2019-10-29 Movidius Limited Systems and methods for head-mounted display adapted to human visual mechanism
US10949947B2 (en) 2017-12-29 2021-03-16 Intel Corporation Foveated image rendering for head-mounted display devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3289169A (en) * 1962-09-27 1966-11-29 Beckman Instruments Inc Redundancy reduction memory
US3346727A (en) * 1966-02-28 1967-10-10 Honeywell Inc Justification of operands in an arithmetic unit
US3646524A (en) * 1969-12-31 1972-02-29 Ibm High-level index-factoring system
US3728684A (en) * 1970-08-05 1973-04-17 Honeywell Inc Dynamic scanning algorithm for a buffered printer

Also Published As

Publication number Publication date
US3919534A (en) 1975-11-11

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