CA1265256A - Apparatus and method for controlling access in a multi-cache data processing system - Google Patents

Apparatus and method for controlling access in a multi-cache data processing system

Info

Publication number
CA1265256A
CA1265256A CA000500923A CA500923A CA1265256A CA 1265256 A CA1265256 A CA 1265256A CA 000500923 A CA000500923 A CA 000500923A CA 500923 A CA500923 A CA 500923A CA 1265256 A CA1265256 A CA 1265256A
Authority
CA
Canada
Prior art keywords
data processing
signal
data
data signal
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA000500923A
Other languages
English (en)
French (fr)
Inventor
Richard A. Warren
Thomas W. Eggers
Stephen J. Shaffer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of CA1265256A publication Critical patent/CA1265256A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)
  • Multi Processors (AREA)
CA000500923A 1985-02-05 1986-02-03 Apparatus and method for controlling access in a multi-cache data processing system Expired - Fee Related CA1265256A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69836685A 1985-02-05 1985-02-05
US698,366 1985-02-05

Publications (1)

Publication Number Publication Date
CA1265256A true CA1265256A (en) 1990-01-30

Family

ID=24804934

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000500923A Expired - Fee Related CA1265256A (en) 1985-02-05 1986-02-03 Apparatus and method for controlling access in a multi-cache data processing system

Country Status (7)

Country Link
US (1) US4982322A (de)
EP (1) EP0194024B1 (de)
JP (1) JPS61246852A (de)
AT (1) ATE80480T1 (de)
AU (1) AU5297286A (de)
CA (1) CA1265256A (de)
DE (1) DE3686660T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE89940T1 (de) * 1986-04-02 1993-06-15 Siemens Ag Verfahren zum ansteuern eines gemeinsamen speichers eines aus einzelnen mikroprozessorsystemen bestehenden mehrprozessorsystems.
JP2511588B2 (ja) * 1990-09-03 1996-06-26 インターナショナル・ビジネス・マシーンズ・コーポレイション デ―タ処理ネットワ―ク、ロックを獲得させる方法及び直列化装置
JPH0785219B2 (ja) * 1990-11-15 1995-09-13 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システム及びデータ制御方法
US5237694A (en) * 1991-05-30 1993-08-17 Advanced Micro Devices, Inc. Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor
US5454082A (en) * 1991-09-18 1995-09-26 Ncr Corporation System for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second bus
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5353343A (en) * 1992-04-30 1994-10-04 Rockwell International Corporation Telephonic switching system with a user controlled data memory access system and method
JP3360933B2 (ja) * 1994-06-01 2003-01-07 富士通株式会社 情報処理システムにおける記憶制御方法および記憶制御装置
JP2003177960A (ja) * 2001-12-12 2003-06-27 Matsushita Electric Ind Co Ltd 演算装置及び記憶装置
US8856003B2 (en) * 2008-04-30 2014-10-07 Motorola Solutions, Inc. Method for dual channel monitoring on a radio device
US8226126B2 (en) * 2009-08-24 2012-07-24 Jpro Dairy International, Inc. Bottle mixing assembly

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735360A (en) * 1971-08-25 1973-05-22 Ibm High speed buffer operation in a multi-processing system
US3833889A (en) * 1973-03-08 1974-09-03 Control Data Corp Multi-mode data processing system
US4073005A (en) * 1974-01-21 1978-02-07 Control Data Corporation Multi-processor computer system
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources
JPS556633A (en) * 1978-06-29 1980-01-18 Nec Corp Memory access control system
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system
US4513367A (en) * 1981-03-23 1985-04-23 International Business Machines Corporation Cache locking controls in a multiprocessor
US4394727A (en) * 1981-05-04 1983-07-19 International Business Machines Corporation Multi-processor task dispatching apparatus
US4567562A (en) * 1983-07-21 1986-01-28 Burroughs Corporation Controller for controlling access to a plurality of records that can be accessed and changed by several independent processors
US4648030A (en) * 1983-09-22 1987-03-03 Digital Equipment Corporation Cache invalidation mechanism for multiprocessor systems
US4604694A (en) * 1983-12-14 1986-08-05 International Business Machines Corporation Shared and exclusive access control
US4622631B1 (en) * 1983-12-30 1996-04-09 Recognition Int Inc Data processing system having a data coherence solution

Also Published As

Publication number Publication date
DE3686660D1 (de) 1992-10-15
JPS61246852A (ja) 1986-11-04
EP0194024A2 (de) 1986-09-10
EP0194024B1 (de) 1992-09-09
ATE80480T1 (de) 1992-09-15
AU5297286A (en) 1986-08-14
US4982322A (en) 1991-01-01
EP0194024A3 (en) 1988-08-03
DE3686660T2 (de) 1993-04-15

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